Setting Up VSS Configuration Files
The .synopsys_vss.setup file contains the mapping information that directs the VHDL System Simulator (VSS) Software to use Altera®-supplied Altera Simulation Libraries during simulation. To configure your environment for the MAX+PLUS® II/Synopsys interface, follow these steps:
- Add the lines shown in Figure 1 to your .synopsys_vss.setup file. Altera provides a sample setup file, .synopsys_vss.setup, in the /usr/maxplus2/synopsys/config directory. See Figure 1.
| Figure 1. Sample .synopsys_vss.setup File |
WORK > DEFAULT
DEFAULT : .
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altera : /usr/maxplus2/synopsys/library/alt_mf/lib
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flex_vtl : /usr/maxplus2/synopsys/library/alt_pre/vital/
lib/flex_vtl
alt_vtl : /usr/maxplus2/synopsys/library/alt_post/sim/
lib/alt_vtl
flex10k_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
lib/flex10k_ftsm
flex10k_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
lib/flex10k_ftgs
max9000_ftsm : /usr/maxplus2/synopsys/library/alt_pre/max9000/
lib/max9000_ftsm
max9000_ftgs : /usr/maxplus2/synopsys/library/alt_pre/max9000/
lib/max9000_ftgs
flex8000_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
lib/flex8000_ftsm
flex8000_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
lib/flex8000_ftgs
max7000_ftsm : /usr/maxplus2/synopsys/library/alt_pre/max7000/
lib/max7000_ftsm
max7000_ftgs : /usr/maxplus2/synopsys/library/alt_pre/max7000/
lib/max7000_ftgs
flex6000_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
lib/flex6000_ftsm
flex6000_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
lib/flex6000_ftgs
max5000_ftsm : /usr/maxplus2/synopsys/library/alt_pre/max5000/
lib/max5000_ftsm
max5000_ftgs : /usr/maxplus2/synopsys/library/alt_pre/max5000/
lib/max5000_ftgs
flex10k_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
lib/flex10k_fpga_ftsm
flex10k_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex10k/
lib/flex10k_fpga_ftgs
max9000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/max9000/
lib/max9000_fpga_ftsm
max9000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/max9000/
lib/max9000_fpga_ftgs
flex8000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
lib/flex8000_fpga_ftsm
flex8000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex8000/
lib/flex8000_fpga_ftgs
max7000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/max7000/
lib/max7000_fpga_ftsm
max7000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/max7000/
lib/max7000_fpga_ftgs
flex6000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
lib/flex6000_fpga_ftsm
flex6000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/flex6000/
lib/flex6000_fpga_ftgs
max5000_fpga_ftsm : /usr/maxplus2/synopsys/library/alt_pre/max5000/
lib/max5000_fpga_ftsm
max5000_fpga_ftgs : /usr/maxplus2/synopsys/library/alt_pre/max5000/
lib/max5000_fpga_ftgs
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The variables in the .synopsys_vss setup file perform the following functions:
- The
WORK variable specifies your working directory, i.e., the directory where you start the Synopsys tools. If not explicitly specified elsewhere, the results of any analysis or compilation are written to this directory. The first line of the file shown in Figure 1 maps WORK to the design library variable called DEFAULT.
- The
DEFAULT variable is used to create library aliases, which allows you to map the WORK variable to various paths. In Figure 1, the DEFAULT variable specifies the current directory.
- The altera library is listed to allow you to simulate the architecture control logic functions in the alt_mf library.
- The remaining lines in the file specify the path and name of the directories that contain the device simulation libraries for Altera device families.
- Analyze the target device simulation library to ensure that the correct timing and functional information is provided to VSS. Analyzing the simulation library produces VSS simulation models of the primitives that appear in all Altera-provided technology libraries.
You can analyze device simulation libraries by using the Altera-provided shell script analyze_vss:
- Add the /usr/maxplus2/synopsys/bin directory, which contains the analyze_vss scripts, to the
PATH environment variable in your .cshrc file.
- Make sure that you have write privileges for the /usr/maxplus2/synopsys/library/alt_pre/<device family> directory because the analyzed model is placed in the /usr/maxplus2/synopsys/library/alt_pre/<device family>/lib directory and the analysis log file is placed in the ./synopsys/library/alt_pre/<device family>/src directory.
- Run the analyze_vss shell script by typing
analyze_vss  at the dc_shell prompt. When you run the analyze_vss shell script, you are prompted to select the appropriate device family simulation model(s) for analysis. Figure 2 shows the analyze_vss shell script.
| Figure 2. The analyze_vss Shell Script
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Type the full pathname of the directory where the MAX+PLUS® II software is installed
(default: /usr/maxplus2):
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| <MAX+PLUS II system directory>
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Analyze VSS Simulation Models:
1. flex10k_FTGS
2. flex10k_FTSM
3. flex10k_fpga_FTGS
4. flex10k_fpga_FTSM
5. max9000_FTGS
6. max9000_FTSM
7. max9000_fpga_FTGS
8. max9000_fpga_FTSM
9. flex8000_FTGS
10. flex8000_FTSM
11. flex8000_fpga_FTGS
12. flex8000_fpga_FTSM
13. max7000_FTGS
14. max7000_FTSM
15. max7000_fpga_FTGS
16. max7000_fpga_FTSM
17. flex6000_FTGS
18. flex6000_FTSM
19. flex6000_fpga_FTGS
20. flex6000_fpga_FTSM
21. max5000_FTGS
22. max5000_FTSM
23. max5000_fpga_FTGS
24. max5000_fpga_FTSM
25. alt_vtl
26. flex_vtl
27. Quit
Enter one or more numbers: <device library numbers>
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- Check the log file to make sure that no errors occurred during the analysis of the simulation models.
- Use VSS to simulate your pre-routed VHDL design.
Related Topics:
- Refer to the VHDL System Simulator Core Programs Manual for more information about VSS.
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