Performing Timing Verification of Verilog Output Files (.vo) with MOTIVE Software
After you have compiled a project and generated a Verilog Output File (.vo) with the MAX+PLUS II Software, you can use Viewlogic MOTIVE to perform timing verification. The MOTIVE timing model library, motive.lib, provides basic primitives and the clklock megafunction for timing verification.
To perform timing verification for Verilog Output Files with MOTIVE software, follow these steps:
Set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.
- Generate a Verilog Output File by compiling your design with the MAX+PLUS II software, as described in Compiling Projects with MAX+PLUS II Software.
- Start the MOTIVE software by typing
motive  at the UNIX prompt. The MOTIVE Session Log and Setup Advisor windows are displayed. Choose OK.
- Choose Project on the vertical menubar in the Setup Advisor, then choose the Name (Select project name) tab and specify the name of the project for Project name. The directory in which you started MOTIVE will be selected automatically for Current directory. Choose Accept. MOTIVE then searches for the <project name>.stm file. If this is a new file, a message will appear in the Session Log window that mentions that MOTIVE found a license and the message
could not open the <project name>.stm file -- assuming a new design.
- Choose Flow from the vertical menubar, then choose the Type (Select flow type) tab. Select the Using Verilog and SDF option and choose Accept.
- Choose Options from the vertical menubar, then choose the Options (Miscellaneous usage options) tab. If desired, specify a different value for the MOTIVE analysis cycle time option. Choose Accept.
- Choose Verilog on the vertical menubar and specify the following Verilog HDL input options:
- Choose the Translate (Translate Verilog netlist file) tab. Specify the name of the MAX+PLUS II-generated Verilog Output File (.vo) for the Verilog netlist option. Choose the Common Options button to display the Common Options dialog box. Select the Special Options option and turn on the Skip Behavioral Constructs option. Type either
pinlist or a period (.) for the Generated pin files option. Choose OK to close the Common Options dialog box and return to the Translate tab.
- Specify the location of the MAX+PLUS II-generated alt_max2.vo file for the Vendor module definition option. Choose the Translate button. The Process Execution Log & Tips dialog box displays the current status of the translation to .pin files. Choose OK after successful translation.
- Choose the Import (Confirm Adding hierarchical blocks) tab. Choose the Import Blocks button. The MOTIVE Interaction Log & Tips dialog displays the current import status. Choose OK after a successful completion.
- Select the Hierarchy (Configure hierarchy options) tab. Type the name of the rootblock for the Rootblock of design option, or choose the Find Rootblock button to display the rootblock name. Choose Accept.
- Choose the Check (Review and/or build the netlist database) tab. Choose the Incremental Build button. The MOTIVE Interaction Log & Tips dialog displays the current build status. Choose OK after a successful completion.
- Select SDF on the vertical menubar, then select the Translate (SDF model preparation) tab. Type <project name>
.sdo for the SDF file option, making sure that you specify the .sdo extension. Type <project name>.ctl for the MPP control file name, and <project name>.idd for the IDD file name.
- Choose the Process SDF File button.
If your project contains the clklock megafunction, use the genmtv utility to back-annotate the MPP Control File and to allow the MPP Control File to recognize the clklock function. The input to the genmtv utility is the Verilog netlist file (.vo). From the /<working directory>/<project name>/<case name> directory, type the following command at the UNIX prompt:
genmtv -v <project name>
- If your project contains RAM or ROM functions and you turned on the Flatten Bus option the MAX+PLUS II Compiler's Verilog Netlist Writer Settings dialog box when you compiled your project, you must edit the mem.lib file, i.e., the MOTIVE Model Pre-Processor timing library file generated with the genmtv utility. You must remove the bracket
[ ] characters from all occurrences of the address bus, e.g., change A[0] to A0, in both the INPUTS and MIXED sections of every RAM and ROM cell definition in mem.lib.
- Select the MPP (MOTIVE model compilation) tab. Type <project name>
.ctl for the Control file option. Type /usr/maxplus2/viewlogic/library/alt_time/motive.lib /usr/maxplus2/viewlogic/library/alt_time/motive.drv for the Libraries option. If the project contains memory functions, you should also specify the location of the mem.lib file for the Libraries option. Type <project name>.mod for the Generated model file option and <project name>.rcf for the Revised control file option. Choose the RUN MMP button. The MOTIVE Execution Log & Tips dialog displays and shows the current status. Choose OK after a successful completion.
- Select Save from the File menu in the Setup Advisor to write all the selections made so far to the <project name>.stm file.
- Select Clock on the vertical menubar, then choose the File (Check reference file and timebase options) tab. The correct name of the Clock Reference File (.ref) should be displayed for the Clock reference file option. Choose Accept.
 |
Every MOTIVE analysis requires a MOTIVE Clock Reference File. If the project is simple, you can create the file in the Setup Advisor. Otherwise, you must create the file with a text editor using MOTIVE syntax. For more information on the purpose, function, and syntax of MOTIVE Clock Reference Files, see the MOTIVE System Reference. |
- Choose the Edit (Simple clock reference generation) tab. Specify the names for the Clock reference and Clock net name options. Choose Generate.
- Choose the Check (Choose incremental definitions) tab, then choose the Load Clock button.
- Choose Finish from the vertical menubar, then choose the Build button. The MOTIVE Interaction Log & Tips dialog displays the current status. Choose OK after a successful completion.
- Select Save from the File menu in the Setup Advisor.
- In the MOTIVE Session Log window, choose Verify (Analyze menu) and then choose the Execute button to start verification. To view the output files, choose Output Files (View menu).
Alternatively, you can run MOTIVE analysis on the command line by following these steps:
- Type the following commands at the UNIX prompt:
vtran <project name>.vo -b -h -u alt_max2.vo (generates .pin files)
sdf2mtv <project name>.sdfo (generates .ctl files)
- If your project contains
ram, rom, dpram, or clklock functions, you should also type the following commands at the UNIX prompt:
genmtv -v <project name>
mmp <project name>.ctl -l /usr/maxplus2/viewlogic/library/alt_time/motive.lib -l /usr/maxplus2/viewlogic/library/alt_time/motive/drv -l mem.lib
- Type the following command at the UNIX prompt:
amtv <project name>
Feedback
Did this information help you?
If no, please log onto mySupport to file a technical request or enhancement.
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
|
文档资料
> 
