Incremental Compilation Resource Center
The Quartus® II incremental compilation feature enables you to reduce compilation times by up to 70 percent while preserving the results of unchanged logic in your design. Incremental compilation supports both top-down and bottom-up team-based design methodologies. For additional information on incremental compilation, see:
For a brief overview of the incremental compilation feature, refer to the Quartus II Incremental Compilation product feature page.
To search for known incremental compilation issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Incremental Compilation Resources
Table 1 provides links to available documentation on incremental compilation.
| Table 1. Incremental Compilation Documentation |
| Title |
Description |
| Design Planning with the Quartus II Software (PDF) |
This chapter of the Quartus II Development Software Handbook discusses important FPGA design planning issues, provides recommendations, and describes various tools available for Altera FPGAs to help you improve design productivity. It describes how planning can improve your success with incremental compilation. |
| Quartus II Incremental Compilation for Hierarchical and Team-Based Design (PDF) |
This chapter of the Quartus II Development Software Handbook describes Quartus II software features and design methodologies for top-down and bottom-up incremental compilation, provides guidelines, and includes various recommended design flows and application examples to help you meet your design goals. |
| AN 470: Best Practices for Incremental Compilation Partitions and Floorplan Assignments (PDF) |
This application note provides a set of guidelines to help you partition your design to take advantage of Quartus II incremental compilation, and to help you create a design floorplan (using LogicLockTM regions) to support the flow. |
Table 2 provides links to available training and demonstrations on incremental compilation.
| Table 2. Incremental Compilation Training and Demonstrations |
| Title |
Description |
Incremental Compilation and Team-Based Design
Online Demonstration |
You will see a demonstration of the incremental compilation feature used in both top-down and bottom-up team-based compilation methodologies.
This is a 10-minute online demonstration.
|
Introduction to Incremental Compilation
Online Course |
You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature. By the end of this training, you will be able to use LogicLock™ regions in physical partitioning of your design. You will be able to segment your design into logical design partitions. You will be able to apply the incremental compilation methodology to both the top-down and bottom-up design flows.
This is a 2-hour online course.
|
Best Practices for Incremental Compilation Partitions and Floorplan Assignments—Part 1 and Part 2
Online Course |
This training explains why and when to use incremental compilation. You will learn how to choose design partitions and follow guidelines to help you set up your design hierarchy and source code for incremental compilation. The training also explains why and when to create a design floorplan for incremental compilation. You will learn how to create a floorplan and follow guidelines to create an optimal floorplan for your design partitions. You will also learn about the tools available for helping with design partitioning, assessing partition quality, and creating a design floorplan in the Quartus II software version 7.2. Finally, you will learn about limitations and restrictions with the incremental compilation feature in the Quartus II software version 7.2.
Parts 1 and 2 are each 1-hour online courses.
|
The Quartus II Software Design Series: Optimization
Instructor-Led Course |
You will learn advanced features of the Quartus II software that enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock regions in the Quartus II software to reduce compilation times and preserve performance.
This is a 1-day instructor-led course.
|
|
文档资料
> 
