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You access this command by pointing to Run EDA Simulation Tool and clicking EDA Gate Level Simulation on the Tools menu. |
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Note: The EDA Gate Level Simulation command is available only after you have performed a full compilation on a project and you specify an EDA simulation tool. If you use this command after the design source files change, the EDA simulation tool runs the simulation with the data from the last compilation. |
Allows you to perform an EDA gate level simulation from within the Quartus II software without recompiling the design. The Quartus II software launches the EDA simulation tool and processes the Quartus II–generated VHDL Output File (.vho) or Verilog Output File (.vo) for the design.
If your design targets a Stratix III or Stratix IV device, in the EDA Gate Level Simulation list you are prompted to select a Timing model. The options appearing in the list indicate whether the timing model is fast or slow, the speed grade of the device, the voltage, and temperature. For example, selecting the "Slow -2 1.1V 85 Model" means you are selecting a slow model for a speed grade 2 device at 1.1 volts and 85 degrees C.
