Test Benches Dialog Box

You open this dialog box by clicking Test Benches in the Simulation page of the Settings dialog box.

Allows you to create, edit, delete, or view a list of test benches.

Allows you to specify the following settings for test bench files used by EDA third party simulation tools:

Test bench name—Requires you to specify the name of the test bench.

Scripting Information

Keyword: eda_test_bench_name

Settings: <string>

Test bench entity—Requires you to specify the entity name of the test bench. This name can be different from the test bench name.

Scripting Information

Keyword: eda_test_bench_module_name

Settings: <string>

Instance—Requires you to specify the instance name of the design in the test bench files.

Scripting Information

Keyword: eda_design_instance_name

Settings: <string>

Run for—(Optional) Allows you to specify the duration of the test bench simulation.

Scripting Information

Keyword: eda_test_bench_run_sim_for

Settings: <time>

Test bench files—Requires you to specify the test bench files included in the test bench. Type or browse to the project directory to select the files to include. You should adjust the file order with the Up and Down buttons so that the files compile in the proper order, that is, files with dependencies listed after the files they rely on. This file order is required to compile the test bench files in the proper order. Test bench files can be Verilog Design File (.v), VHDL Design File (.vhd), Verilog Test Bench File (.vt), or VHDL Test Bench File (.vht).

Note: Verilog Test Bench Files and VHDL Test Bench Files are essentially Verilog Design Files and VHDL Design Files, respectively, with different extensions to indicate that they are test bench files.

Scripting Information

Keyword: eda_test_bench_file

Settings: <file name>

Allows you to delete the selected test bench.