Specifying Options for Running Simulation Software with a Test Bench

To specify options for simulating with a test bench in ModelSim, ModelSim-Altera, Active-HDL, Riviera-PRO, NCSim (NC-Verilog or NC-VHDL), VCS, or VCS MX:

1. On the Assignments menu, click Settings.

2. In the Category list, select Simulation under EDA Tool Settings.

3. Select ModelSim, ModelSim-Altera, Active-HDL, Riviera-PRO, NCSim, VCS, or VCS MX in the Tool name list.

4. If you selected ModelSim, ModelSim-Altera, Active-HDL, Riviera-PRO, or NCSim, you have the option to turn on Run gate-level simulation automatically after compilation.

5. In the Format for output netlist list, select either VHDL or Verilog HDL.

6. In the Output directory box, type or browse to the location where you want output files saved.

7. If you want to map illegal HDL characters, turn on Map illegal HDL characters.

8. To filter glitches in Verilog Output Files (.vo) and VHDL Output Files (.vho), and the corresponding Standard Delay Format Output File (.sdo), turn on Enable glitch filtering.

9. To specify options for creating a script to generate a Value Change Dump File (.vcd) file with an EDA simulation tool:

   1. Turn on Generate Value Change Dump (VCD) file script.

   2. Under Script settings, specify the type of output signals to include in the Value Change Dump File generation script and the name of the test bench instance for which you are performing the simulation.

   3. If you are running your simulation with a test bench selected under NativeLink settings, the design instance name must be identical to what you specify for the test bench; otherwise NativeLink simulation does not generate a Value Change Dump file.

10. Click the More EDA Netlist Writer Settings button to choose from a list of other options:

11. 1. Type the name you want to direct the EDA Netlist Writer to use for the Architecture name in the VHDL output netlist in the Setting box.

    2. If you want to add the devpor, devclrn, and devoe signals as input ports in the top-level design hierarchy in the Verilog Output File or VHDL Output File, turn on Bring out device-wide set/reset signals as ports.

    3. If you want to disable setup and hold violation detection in bi-directional pins, turn on Disable detection of setup and hold violations detection in input registers of bi-directional pins

    4. If you want to disable writing the entity definition of top-level entity into the VHDL file, turn on Do Not Write Top Level VHDL Entity.

    5. If you want to flatten all buses when creating the Verilog Output File or VHDL Output File, turn on Flatten buses into individual nodes.

    6. If you want to generate a Verilog Output File or VHDL Output File for a functional simulation, turn on Generate netlist for functional simulation only.

    7. If you want to maintain the original design hierarchy in the Verilog Output File or VHDL Output File, turn on Maintain hierarchy.

    8. If you want to truncate hierarchical node names to 80 characters or more, turn on Truncate long hierarchy paths.

    9. Click OK.

11. Click the More NativeLink Settings button to choose from a list of other options:

12. 1. Generate third-party EDA tool command scripts without running the EDA tool.

    2. Launch third-party EDA tool in command-line mode.

    3. Location of user compiled simulation library. Do not use this option to specify the directory for ModelSim-Altera software precompiled libraries or Active-HDL precompiled libraries.

    4. Click OK.

12. Turn on Compile test bench.

13. If you have not already created test benches, click the Test Benches button.

14. In the Test Benches dialog box, click the New button.

15. Create one or more new test benches in the New Test Bench Settings dialog box:

16. 1. In the Test bench name box, type the name of the test bench you want to create.

    2. In the Test bench entity box, type the name of the test bench entity. This instance name can be different than the test bench name.

    3. In the Instance box, type the name of the instance. This entity name can be different than the test bench name.

    4. In the Run for box, type the simulation time and select the time units.

    5. Type or browse in the File name box to select files that are included in the test bench. The file types supported include Verilog Design File (.v), VHDL Design File (.vhd), Verilog Test Bench File (.vt), or VHDL Test Bench File (.vht).

• 6. Click Up or Down to arrange the files in order of dependency.

  7. Click OK.

15. In the Compile test bench list, select the test bench you want to compile.

16. To use a script to set up the simulation:

    1. Turn on Use script to setup simulation

    2. Type or browse to the location of the Mentor Graphics ModelSim Macro File (.do), Tcl Script File (.tcl), or batch file that contains the simulation commands.

1. 3. Click OK.

17. If you are using the ModelSim or ModelSim-Altera simulation software and want to use a script to compile a test bench:

18. 1. Select Script to compile test bench:

    2. Type or browse to the location of the Mentor Graphics ModelSim Macro File, Tcl Script File, or batch file that contains the script.