You can use the Quartus II PowerPlay Power Analyzer to perform power analysis of a design after performing a simulation of the design in other EDA simulation tools. The EDA Netlist Writer generates a script file which you can run in an EDA simulation tool to generate a Value Change Dump File (.vcd). You can then use the Value Change Dump File as input to the power analyzer to perform power analysis. The Cadence NC-Verilog and NC-VHDL, the Synopsys VCS, and the Mentor Graphics ModelSim-Altera and ModelSim PE/SE software support this functionality.
To perform power analysis using the Quartus II software and other EDA simulation tools:
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To specify EDA tool settings in the Quartus II software:
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On the Assignments menu, click Settings.
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In the Category list, select Simulation under EDA Tool Settings.
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In the Tool name list, select the name of the simulation tool.
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To filter glitches in Verilog Output Files (.vo), VHDL Output Files (.vho), and the corresponding Standard Delay Format Output Files (.sdo), turn on Enable glitch filtering.
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Turn on Generate Value Change Dump file script.
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Under Script options, specify the type of output signals to include in the Value Change Dump File generation script and the name of the test bench instance for which you are performing the simulation.
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Compile the design with the Quartus II software.
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Note: For ModelSim, NC-Verilog and NC-VHDL, the EDA Netlist Writer generates a Tcl Script File (.tcl) that you can source in the tool to generate the Value Change Dump File. For VCS, the EDA Netlist Writer generates a Verilog Design File (.v) that you can include in the simulation test bench file.
If you specified that the Quartus II software should run the simulation tool automatically after compilation, the Value Change Dump File is automatically generated during simulation.
If you have already compiled the design, and want to specify different EDA tools settings and generate a Verilog Output File (.vo), VHDL Output File (.vho), and Standard Delay Format Output File (.sdo) without recompiling the design, you can use the Start EDA Netlist Writer command. You can also use the Start EDA Netlist Writer command to generate script files to generate Value Change Dump File in EDA simulation tools. |
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Direct the EDA simulation tool to generate a Value Change Dump File during timing simulation and then perform a timing simulation. For more information, refer to the following topics:
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After generating the Value Change Dump File, perform power analysis in the Quartus II software.
