In the Tool name list, select the name of the simulation tool or select Custom.
Note: If you select a specific EDA tool, the Compiler selects the default Verilog HDL output settings or VHDL output settings for that tool.
You can select Custom to use customized settings.
If you are using the version of the ModelSim software installed as part of the Quartus II software, specify ModelSim-Altera as the simulation tool. If you are using the full version of the ModelSim software, specify ModelSim as the simulation tool.
After you compile the design, a VHDL Output File (.vho) or a Verilog Output File and a Standard Delay Format Output File are created and placed in an tool-specific directory. If you turned on Generate netlist for functional simulation only, a Standard Delay Format Output File is not created.
The Quartus II software creates the tool specific directory located in the simulation directory in the current project directory during compilation. This directory uses the name of the specified EDA simulation tool or custom if you specify Custom.
If you use the default <None> selection, no settings are defined, and no output files are generated.
To run a gate-level simulation automatically after compilation, turn on Run gate-level simulation automatically after compilation.
In the Format for output netlist list select either VHDL or Verilog.
In the Output directory box type or browse to the location where you want output files saved.
In the Time scale list, select a time scale.
If you want to map illegal HDL characters, turn on Map illegal HDL characters.
To filter glitches in Verilog Output Files, VHDL Output Files, and the corresponding Standard Delay Format Output File, turn on Enable glitch filtering.
To specify options for creating a script to generate a Value Change Dump File (.vcd) file with an EDA simulation tool:
Turn on Generate Value Change Dump File script.
Under Script settings, specify the type of output signals to include in the Value Change Dump File generation script and the name of the test bench instance for which you are performing the simulation.
If you are running your simulation with a test bench selected under NativeLink settings, the design instance name must be identical to what you specified for the test bench; otherwise NativeLink simulation will not generate a Value Change Dump File.
Click the More Settings button to choose from a list of other options:
Type the name you want to direct the EDA Netlist Writer to use for the Architecture name in the VHDL output netlist in the Setting box.
If you want to add the devpor, devclrn, and devoe signals as input ports in the top-level design hierarchy in the Verilog Output File or VHDL Output File, turn on Bring out device-wide set/reset signals as ports.
If you want to disable setup and hold violation detection in bi-directional pins, turn on Disable setup and hold time violations detection in input registers of bi-directional pins.
If you want to disable writing the netlist for the top-level entity into the VHDL file, turn on Do Not Write Top Level VHDL Entity.
If you want to flatten all buses when creating the Verilog Output File or VHDL Output File, turn on Flatten buses into individual nodes.
If you want to generate a Verilog Output File or VHDL Output File for a functional simulation, turn on Generate netlist for functional simulation only.
If you want to maintain the original design hierarchy in the Verilog Output File or VHDL Output File, turn on Maintain hierarchy.
If you want to truncate hierarchical node names to 80 characters or more, turn on Truncate long hierarchy paths.
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