Altera Functional Simulation Libraries

Library

Description

220model.v
220model.vhd
220model_87.vhd

Libraries that contain simulation models for Altera library of parameterized modules (LPM) version 2 2 0.

For VHDL-93 compliant designs, use 220model.vhd. For VHDL-87 compliant designs, use 220model_87.vhd.

220pack.vhd

Libraries that contain VHDL Component Declarations for the 220model.vhd library.

altera_primitives.v

altera_primitives.vhd

altera_primitives_components.vhd

Libraries that contain primitives for Altera-specific megafunctions used in Block Design Files (.bdf), AHDL Text Design Files (.tdf), VHDL Design Files (.vhd), and Verilog Design Files (.v).

altera_mf.v
altera_mf.vhd
altera_mf_87.vhd

Libraries that contain simulation models for Altera-specific megafunctions.

For VHDL-93 compliant designs, use altera_mf.vhd. For VHDL-87 compliant designs, use altera_mf_87.vhd.

arriagx_hssi_atoms.v
arriagx_hssi_atoms.vhd

Libraries that contain simulation models for Arria GX designs that contain the alt2gxb megafunction.

For Verilog HDL designs, you must compile the 220model.v and sgate.v simulation model libraries (in that order) before compiling this library.

For VHDL designs, you must compile the 220pack.vhd, 220model.vhd, sgate_pack.vhd, and sgate.vhd simulation model libraries (in that order) and then compile the arriagx_hssi_components.vhd.

arriaii_hssi_atoms.v
arriaii_hssi_atoms.vhd

Libraries that contain simulation models for Arria II GX designs that contain the alt4gxb megafunction.

For Verilog HDL designs, you must compile the 220model.v and sgate.v simulation model libraries (in that order) before compiling this library.

For VHDL designs, you must compile the 220pack.vhd, 220model.vhd, sgate_pack.vhd, and sgate.vhd simulation model libraries (in that order) and then compile the arriaii_hssi_components.vhd.

stratixgx_mf.v
stratixgx_mf.vhd

Libraries that contain simulation models for Stratix GX designs that contain the altgxb megafunction.

For Verilog HDL designs, you must compile the 220model.v and sgate.v simulation model libraries (in that order) before compiling this library.

For VHDL designs, you must compile the 220pack.vhd, 220model.vhd, sgate_pack.vhd, and sgate.vhd simulation model libraries (in that order) before compiling these libraries.

stratixiigx_hssi_atoms.v
stratixiigx_hssi_atoms.vhd

Libraries that contain simulation models for Stratix II GX designs that contain the alt2gxb megafunction.

For Verilog HDL designs, you must compile the 220model.v and sgate.v simulation model libraries (in that order) before compiling this library.

For VHDL designs, you must compile the 220pack.vhd, 220model.vhd, sgate_pack.vhd, and sgate.vhd simulation model libraries (in that order) and then compile the stratixiigx_hssi_components.vhd.

stratixiv_hssi_atoms.v
stratixiv_hssi_atoms.vhd

Libraries that contain simulation models for Stratix IV GX designs that contain the alt4gxb megafunction.

For Verilog HDL designs, you must compile the 220model.v and sgate.v simulation model libraries (in that order) before compiling this library.

For VHDL designs, you must compile the 220pack.vhd, 220model.vhd, sgate_pack.vhd, and sgate.vhd simulation model libraries (in that order) and then compile the stratixiv_hssi_components.vhd.

Note:

• If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
   

• If your design contains the alt2gxb megafunction or the altgx megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb or altgx megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that it can be registered by tx_clkout and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.
   

• If your design contains the alt4gxb megafunction, for a top-level design, you must connect reconfig_togxb[] to a reconfiguration controller because of silicon requirements. For functional simulation or module level simulation, you must assign reconfig_togxb[3:0] to a value of 4'b0010 if you do not have a reconfiguration controller in the same scope. If you do not connect ports and provide them with appropriate initial values, functional simulation fails: rx_analogreset is ignored and rx_pll may not function properly.