Board-Level Page (Settings Dialog Box)

You open this dialog box by clicking EDA Tool Settings in the Settings dialog box, and then clicking Board Level.

Allows you to specify an EDA board-level symbol generation, signal integrity, or timing analysis tool and specify the output directory.

Board-Level Symbol Files:

Allows you to select Viewdraw to generate PartMiner edaXML-Format File (.xml), or select FPGA Xchange to generate an FPGA Xchange-Format File (.fx for symbol generation and board-level verification with other EDA tools.

Scripting Information

Keyword: eda_board_design_symbol_tool

Settings: "FPGA Xchange (Symbol)" | "Viewdraw (Symbol)" | "<None>"

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Board-Level Signal Integrity Analysis Output Files:

Board-Level Signal Integrity Analysis—Allows you to select IBIS to generate an IBIS Output File (.ibs) or HSPICE to generate HSPICE Simulation Deck Files (.sp).

Note: IBIS model generation is fully supported for all devices supported by the Quartus II software, except HardCopy II, MAX II and Stratix II devices. For additional IBIS model device support and support files, refer to the "IBIS models" section of the Device Support section on the Altera website.

HSPICE model generation is supported for only Stratix II single-ended I/O standards.

Scripting Information

Keyword: eda_board_design_signal_integrity_tool

Settings: "IBIS (Signal Integrity)" | "HSPICE (Signal Integrity)" | "<None>"

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Board-Level Timing Analysis Output Files:

Board-Level Timing Analysis—Allows you to select STAMP to create a Stamp model file for use with the Mentor Graphics Tau timing analysis tools.

Scripting Information

Keyword: eda_board_design_timing_tool

Settings: "Stamp (Timing)" | "<None>"

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Specifying the Output Directory for Board-Level Tools :

Type or browse to the location you want to use as the output directory for the selected EDA tool. The default name contains the type of tool or output format, followed by the tool name. For example, the default value for the ModelSim simulation software is simulation/modelsim, the default value for the board-level signal integrity analysis output format IBIS is board/ibis.

Scripting Information

Keyword: eda_netlist_writer_output_dir

Settings: <directory path>

If you select IBIS as your output format, you can turn on Enable model selector to generate all possible models for each I/O cell in the IBIS file. The default setting lists one model per I/O cell.

Scripting Information

Keyword: eda_ibis_model_selector

Settings: on | off

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