Design Entry and Synthesis Page (Settings Dialog Box)

You open this dialog box by clicking EDA Tool Settings in the Settings dialog box, and then clicking Design Entry/Synthesis.

Allows you to specify options for processing files generated by other EDA design entry or synthesis tools.

If you select a specific tool in the Tool name list, the default VCC and GND signal names for that tool appear under Signal names, and the Altera-provided Library Mapping File (.lmf) for that tool is shown under Library Mapping File. You can type new signal names in the VCC and GND boxes under Signal names, or specify a different Library Mapping File in the File name box. The setting for the Tool name is automatically copied to the settings for any new project you create, so that you do not need to re-enter it every time you create a new project.

Tool name:

Specifies the EDA tool you are using for design entry and synthesis; simulation; timing analysis; board-level signal integrity, timing or symbol generation; or physical synthesis.

Scripting Information

Keyword: eda_design_entry_synthesis_tool

*default

Format:

Displays a list of available input synthesis formats for your selected EDA input tool. Depending on which synthesis formats your tool supports, available formats can include Verilog HDL, VHDL, AHDL, EDIF Input File (.edf) or Verilog Quartus Mapping File (.vqm).

Scripting Information

Keyword: eda_input_data_format

Settings: "VQM" | "Verilog HDL" | "VHDL" | "EDIF" | AHDL

Run this tool automatically to synthesize the current design:

Directs the Quartus II software to run the selected design entry/synthesis tool in command-line mode. The Quartus II software uses a Tcl Script File (.tcl) to synthesize the design in the EDA design entry/synthesis tool and generate an EDIF Input File (.edf) or Verilog Quartus Mapping File (.vqm) for the design. The Quartus II software then compiles the EDIF Input File or Verilog Quartus Mapping File.

Scripting Information

Keyword: eda_run_tool_automatically

Settings: on | off

*default

Signal names:

Specifies the signal names for VCC or GND used in the files generated by the EDA design entry or synthesis tool.

VCC—Specifies the global high signal used in the files generated by the EDA design entry or synthesis tool. The default name is either VCC or the name typically used by the tool as specified in the Tool name box. Type one or more signal names with up to 20 total name characters. Separate multiple signal names by either commas (,) or spaces.

Scripting Information

Keyword: eda_input_vcc_name

Settings: <signal name>

default = vcc

GND—Specifies the global low signal used in the files generated by the EDA design entry or synthesis tool. The default name is either GND or the name typically used by the tool as specified in the Tool name box. Type one or more signal names of up to 20 total name characters. Separate multiple signal names by either commas (,) or spaces.

Scripting Information

Keyword: eda_input_gnd_name

Settings: <signal name>

default = gnd

Library Mapping File:

Specifies Altera-provided Library Mapping Files (.lmf) used by the Quartus II software in compiling EDIF Input Files (.edf), VHDL Design Files (.vhd), or Verilog Design Files (.v) that contain non-Quartus II functions that require mapping to Quartus II functions.

You can specify the full path name of the Library Mapping File in the File name box, or you can browse to locate the Library Mapping File.

Turn on Show information messages describing LMF mapping during compilation if you want to display information about Library Mapping File mapping in the Messages window during compilation.

Scripting Information

Keyword: eda_lmf_file

Settings: <file name>