You open this dialog box by clicking EDA Tool Settings in the Settings dialog box, and then clicking Simulation.
Allows you to specify options for generating VHDL Output File (.vho), Verilog Output File (.vo) and corresponding Standard Delay Format Output Files (.sdo). You can also select options for generating a script file that you can use to generate a Value Change Dump File (.vcd) for use with other EDA simulation tools. If you select a specific EDA simulation tool, the EDA Netlist Writer selects the default settings for that tool. You can change the settings in this dialog box, and you can click Reset to restore settings to the original defaults. If you have defined customized settings previously, you can select Custom in the Tool name list to use those option settings.
The following options modify how and where the EDA Netlist Writer generates output files.
Time scale—Directs the EDA Netlist Writer to represent timing delays with the specified time units in each Verilog Output File or Standard Delay Format Output Files. The selected value for the Time Scale option may be between 1 picosecond and 1 millisecond.
Note: Altera recommends Time scale settings in picoseconds (ps) when performing timing simulations of designs containing RAM.
Scripting Information
Keyword:eda_time_scale
Settings: <time value between 1 picosecond and 1 millisecond>
*default
Format for output netlist—Allows you to select VHDL or Verilog HDL as the format for the netlist output of the active simulation or timing tool. Select VHDL to generate EDA Netlist Writer VHDL Output Files, and Verilog to generate Verilog Output Files.
Output directory—Type or browse to the location you want to use as the output directory for the specified EDA simulation tool. The default name contains the type of tool or output format, followed by the tool name. For example, the default value for the ModelSim simulation software is simulation/modelsim.
Scripting Information
Keyword:eda_netlist_writer_output_dir
Settings: <output directory>
*default
Map illegal HDL characters—Turning this option on directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL.
If you selected VHDL in the Format for output netlist list, the EDA Netlist writer maps non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to (_a) in VHDL Output Files. This option generates VHDL 1987 compatible names.
If you selected Verilog HDL in the Format for output netlist list, the EDA Netlist writer maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus II hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files. Turning on this option also maps other illegal non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to underscore (_).
Scripting Information
Keyword:eda_map_illegal_characters
Settings: on | off
*default
Enable glitch filtering—Turning this option on directs the EDA Netlist Writer to perform glitch filtering when generating VHDL Output Files, Verilog Output Files, and the corresponding Standard Delay Format Output Files for use with other EDA simulation tools. This option is available only for MAX II and Stratix II designs.
During simulation, a glitch occurs when transitions of a signal occur too quickly to allow the signal to fully propagate over the routing between the source and destination ports. Glitch filtering removes all pulses that are shorter than the glitch interval length, allowing for more accurate reporting of signal transitions during simulation. The glitch filtering enabled by this option only removes glitches that occur over device routing.
You can also use this option to produce more accurate power analysis results when you us a Value Change Dump File generated by an EDA simulation tool while performing power analysis in the Quartus II PowerPlay Power Analyzer.
Generate Value Change Dump (VCD) file script—Directs the EDA Netlist Writer to generate a script file that you can use to generate a Value Change Dump File in other EDA simulation tools. You can use the script to generate a Value Change Dump file when performing a simulation with the ModelSim, ModelSim-Altera, NCSim, or VCS software.
Scripting Information
Keyword:eda_write_nodes_for_power_estimation
Settings: off | all_nodes | no_combinational_output
*default
Script settings—Opens the Script Settings dialog box which allows you to specify the signals that are included in the script file used to generate a Value Change Dump File in other EDA simulation tools. These signals are monitored and written out to the Value Change Dump File during simulation. The options for script settings are:
All signals—Directs the EDA Netlist Writer to include all output signals for entities and nodes in the design. Depending on the size of your design, this option may result in an extremely large Value Change Dump File.
All output signals except combinational lcell outputs—Directs the EDA Netlist Writer to include all output signals for entities and nodes in the design, except combinational outputs. This option results in a smaller Value Change Dump File. Altera recommends this option if your design targets a MAX II or Stratix II device with the Vectorless estimation option during power analysis.
Scripting Information
Keyword:eda_write_nodes_for_power_estimation
Settings: off | all_nodes | no_combinational_output
*default
Design instance name—Specifies the test bench design instance name for simulation in EDA simulation tools. This option allows the EDA Netlist Writer to include the full path of the output signals in the script to generate the Value Change Dump File.
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Scripting Information
