|
This option can be set in the Assignment Editor, or you can set this option in the Analysis & Synthesis Settings page in the Settings dialog box. |
A logic option that allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the functionality of the design.
This option is useful for finding areas of the design that can be implemented more efficiently, and as a result, minimizing the area and maximizing the speed of the design.
This option must be assigned to a design entity or it is ignored. This option is available for supported device families: ACEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Arria GX, Cyclone, Cyclone II, Cyclone III, FLEX 10K, FLEX 10KA, FLEX 10KE, HardCopy, Stratix, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix GX.
|
|
|
Settings: on | off *default |
Scripting Information
