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This option can be set in the Assignment Editor, or you can set this option by clicking More Settings on the Analysis & Synthesis Settings page in the Settings dialog box. |
A logic option that allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps megafunction. The shift registers must all use the same clock and clock enable signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart.
This option is useful for finding areas of the design that can be implemented more efficiently, and as a result, minimizing the area and maximizing the speed of the design.
This option must be assigned to a design entity or it is ignored. This option is available for supported device families: APEX 20K, APEX 20KC, APEX 20KE, APEX II, Arria GX, Cyclone, Cyclone II, Cyclone III, HardCopy, HardCopy Stratix, MAX II, Stratix, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix GX.
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Settings: auto | always | off *default |

Scripting Information