An ASCII text file (with the extension .sp) that contains an HSPICE Simulation Deck for a specific pin, generated by the Quartus II software for performing board-level signal integrity verification of Altera devices with other EDA tools.
An HSPICE Simulation Deck includes a physical description of a circuit and the conditions under which to simulate the circuit. The physical description includes a list of circuit elements and the connectivity between the elements. Additionally, voltage and current sources may be included that provide stimulus to the circuit. Simulation of this circuit is meant to provide data relevant timing, power, and signal integrity analysis.
The Quartus II software can generate HSPICE Simulation Deck files for designs that target the Stratix II device family for all I/O standards and the Stratix II GX device family for all I/O standards except for high-speed transceivers.
For Stratix II, the HSPICE Writer is able to generate HSPICE Simulation Deck files for every single-ended I/O in a design. Each HSPICE Simulation Deck is automatically configured to implement settings and assignments made to the relevant pin and is ready for simulation in HSPICE 2003.9-SP1 or higher with the Stratix II I/O Buffer Encrypted HSPICE Models.
You can direct the Compiler to generate an HSPICE simulation deck file after successful compilation by selecting HSPICE in the Board-Level Signal Integrity Analysis section of the Board-Level page of the EDA Tool Settings dialog box. The Compiler places the generated HSPICE Simulation Deck file in the /<project directory>/board/hspice directory by default. The file name of the HSPICE Simulation Deck file is <pin_name>_<signal_name>_<in/out>.sp. For bidirectional pins, the HSPICE Writer produces both an input and output HSPICE Simulation Deck file.
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