A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) standard netlist file (with the extension .vho) that is generated by the Quartus II Compiler.
The Quartus II Compiler can generate several types of VHDL Output Files, one type for each particular EDA tool. VHDL Output Files can be generated for simulation tools and timing analysis tools. The VHDL Output File cannot be compiled with the Quartus II Compiler.
You can specify that the Compiler generates a VHDL Output File after successful compilation by selecting the name of the specific VHDL simulation or timing analysis tool or by selecting Custom VHDL from the Tool name list and specifying options in the Simulation or Timing Analysis pages of the Settings dialog box.
You can also generate a VHDL Output File by using the Start EDA Netlist Writer command. You can use this command if you have already compiled the design and want to change the EDA tool settings and generate a VHDL Output File for another EDA tool.
The Compiler places the generated VHDL Output File into a tool-specific directory within the current project directory by default. For EDA simulation tools, the VHDL Output File is placed in the /<project directory>/simulation/<EDA simulation tool> directory. For EDA timing analysis tools, the VHDL Output File is placed in the /<project directory>/timing/<EDA timing analysis tool> directory. If you select Custom VHDL for simulation or timing analysis, the VHDL Output File is placed in the /<project directory>/simulation/custom directory or /<project directory>/timing/custom directory, respectively.
The file name of the VHDL Output File is the top-level design entity name with a .vho extension. The file name of the Standard Delay Format Output File (.sdo) is the top-level design entity name with a "_vho" appended to the project name and an .sdo extension (for example, <top-level design name>_vho.sdo).
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