Mapping to Libraries and Compiling Design Files with the ModelSim-Altera Software

To map to the ModelSim precompiled libraries (for VHDL designs) and compile the Verilog Output Files (.vo) or VHDL Output File (.vho) and test bench files in the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, using command-line commands:

1. If you have not already done so, set up a ModelSim project with command-line commands.

2. For VHDL designs, to map to the ModelSim precompiled libraries, type the following command at the ModelSim prompt:

   vmap <device family>\<ModelSim-Altera install directory>\altera\vhdl\<device family>\ 

    

   Note: For VHDL 87-compliant designs for APEX 20KE devices, you must map to the \<ModelSim-Altera install directory>\altera\vhdl\apex20ke_87\ directory.

    

3. If your design contains the altgxb megafunction, to map to the precompiled Stratix GX timing simulation model libraries type the following command at the ModelSim prompt:

   vmap stratixgx_gxb \quartus\eda\sim_lib\modelsim\<verilog | vhdl>\stratixgx_gxb\ 

    

   Note: If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high. If your design contains the alt2gxb megafunction or altgxb instantiations, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that it can be registered by tx_clkout and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

    

4. To compile the Verilog or VHDL Output File and test bench files (if you are using a test bench) into the working directory:

   For VHDL designs:

   vcom -work work <path to library>\altera_primitves.vhd (If your design targets a Stratix III or Cyclone III device.)
   vcom -work work <path to library>\altera_primitves_components.vhd (If your design targets a Stratix III or Cyclone III device.)
   vcom -work work <design name>.vho 
   vcom -work work <test bench>.vhd 

   For Verilog designs:

   vlog -work work <path to library>\altera_primitves.vhd (If your design targets a Stratix III or Cyclone III device.)
   vlog -work work <path to library>\altera_primitves_components.vhd (If your design targets a Stratix III or Cyclone III device.)
   vlog -work work <design name>.vo
   vlog -work work <test bench>.v 

    

To continue with the ModelSim-Altera simulation flow, perform a timing simulation with the ModelSim-Altera software.