Performing a Functional Simulation with the ModelSim-Altera Software

You can use the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components with the ModelSim-Altera interface, or with command-line commands.

If you have not already done so, set up a project with the ModelSim-Altera software.
To compile the Verilog or VHDL Design Files and test bench files (if you are using a test bench):

On the Compile menu, click Compile.
In the Library list of the Compile HDL Source Files dialog box, select the work library.
In the File name list, type the directory path and file name of the Verilog or VHDL Design File.

or

In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog or VHDL Design File.

Note: If you have generated a VHDL Output File (.vho) or Verilog Output File (.vo) for use in a functional simulation, you should compile it before proceeding.

Click Compile.
Repeat steps 2b to 2d to compile the test bench file(s).
Click Done.

To load the design:
1. On the Simulate menu, click Simulate. The Simulate dialog box appears.
2. If you are simulating a Verilog design, to specify the ModelSim precompiled libraries:
  1. Click the Libraries tab.
  2. In the Search Libraries (-L) box, click Add.
  3. Specify the \<ModelSim-Altera install directory>\altera\verilog\220model\ directory.
  4. Repeat step iii to add the \<ModelSim-Altera install directory>\altera\verilog\altera_mf\ directory.
  5. Click OK.
3. In the Name list, click the + icon to expand the work directory.
4. Select the top-level design file to simulate.
5. Click Add.
6. Click Load.
Perform the functional simulation in the ModelSim-Altera software.

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

To use the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components using command-line commands:

If you have not already done so, set up a ModelSim-Altera project with command-line commands.

If your design contains the altgxb megafunction, to map to the precompiled Stratix GX functional simulation model libraries type the following command at the ModelSim prompt:

vmap altgxb \<ModelSim-Altera install directory>\altera\<verilog or vhdl>\altgxb\

Note:

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that it can be registered by tx_clkout and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

To map the VHDL-87-compliant design libraries, type the following commands at the ModelSim prompt:

vmap lmf \<ModelSim-Altera install directory>\altera\220model_87\ vmap altera_mf \<ModelSim-Altera install directory>\altera\altera_mf_87\
To compile the Verilog or VHDL Design Files and test bench files (if you are using a test bench), type the following commands at the ModelSim prompt.

For VHDL designs:

vcom -work work<design name>.vhd vcom -work work<test bench>.vhd

For Verilog HDL designs:

vlog -work work<design name>.v vlog -work work<test bench>.v
To load the design, type the following commands at the ModelSim prompt.

For VHDL designs:

vsim work.<top-level design entity>

For Verilog designs:

vsim -L \<ModelSim-Altera install directory>\altera\verilog\220model\ -L \<ModelSim-Altera install directory>\altera\verilog\altera_mf\ work.<top-level design entity>
Perform the functional simulation in the ModelSim-Altera software.

Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the ModelSim-Altera or ModelSim PE or SE main window into a text file and name the file with a .do extension (that is, <file name>.do). Use this script to recompile the libraries if you update them.

To run a macro script:

From the Mentor Graphics ModelSim main window, click Execute Macro.
In the Execute Do File dialog box, locate your ModelSim macro file (.do).
Click Open.