Performing a Timing Simulation with the ModelSim-Altera Software

You can perform a timing simulation of a Verilog or VHDL design with the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, from the ModelSim-Altera interface, or with command-line commands.

To compile the Verilog or VHDL Output File and test bench files (if you are using a test bench) into the working directory:
1. On the Compile menu, click Compile .
2. In the Library list of the Compile HDL Source Files dialog box, select the work library.
3. In the Files of Type list, select All Files (*.*), and in the Look in list, select the name of the Verilog or VHDL Output File.
4. Click Compile.
5. Repeat steps 1b to 1d for the test bench file (if you are using one) that instantiates the Verilog or VHDL Output File.
6. Click Done.

If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
On the Simulate menu, click Simulate. The Simulate dialog box appears.
If you are simulating a Verilog design, click the Verilog tab. Under Pulse Options, type 0 in the Error Limit and Rejection Limit boxes.
If you are simulating a VHDL design, to specify the Standard Delay Format Output File (.sdo):
1. Click the SDF tab.
2. Click Add.
3. In the Add SDF Entry dialog box, click Browse. The Select SDF File dialog box appears.
4. In the Files of type list, select All Files (*.*).
5. Select the Standard Delay Format Output File.
6. Click Open.
7. Click OK.

Note: If you are using a test bench file to provide simulation stimuli to your design, in the Apply to region box, specify the path to the design instance in the test bench, starting from the top-level design file.

If you are simulating a Verilog design, to specify the ModelSim precompiled libraries:
1. Click the Libraries tab.
2. In the Search Libraries (-L) box, click Add.
3. Specify the \<ModelSim-Altera install directory>\altera\verilog\<device family>\ directory.
4. Click OK.
Click the Design tab.
In the Name list, click the + icon to expand the work directory and select the design entity that corresponds to the Standard Delay Format Output File.
Click Add.
Select the top-level design file or test bench.
Click Add.
If you are simulating high-speed circuits (including designs that use HSSI, LVDS, or PLLs):
1. Click the Other tab.
2. In the Other options box type +transport_int_delays and +transport_path_delays.
3. Click OK.
Click Load.
To direct the ModelSim-Altera software to generate a Value Change Dump File (.vcd) that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer, type the following command at the ModelSim prompt:

source<test bench or design instance name>_dump_all_vcd_nodes.tcl

The Tcl Script File directs the ModelSim-Altera software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.
Perform the timing simulation in the ModelSim-Altera software.

Note: You can use batch files to set up and compile each of the libraries automatically. Place all the commands displayed in the ModelSim-Altera or ModelSim PE or SE main window into a text file and name the file with a .do extension (that is, <file name>.do). Use this script to recompile the libraries if you update them.

To run a macro script:

From the Mentor Graphics ModelSim main window, chose Execute Macro.
In the Execute Do File dialog box, locate your ModelSim macro file (.do).
Click Open.

If you have not already done so, map tolibraries and compil design files with the ModelSim-Altera software.
If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
Type the following commands at the ModelSim prompt to load the design with minimum, typical, or maximum timing values.

For VHDL designs:

vsim -sdf(min | typ | max) +transport_int_delays +transport_path_delays /=<design name>.sdo work.<top-level design entity>

For Verilog designs:

vsim +transport_int_delays +transport_path_delays -L \<ModelSim-Altera install directory>\altera\verilog\lpm\ <Modelsim-Altera install directory>\altra\verilog\<<device family>>\ -sdf(min | typ | max) work.<top-level design entity>

To direct the ModelSim-Altera software to generate a Value Change Dump File (.vcd) that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer, type the following command at the ModelSim prompt:

source<test bench or design instance name>_dump_all_vcd_nodes.tcl

The Tcl Script File directs the ModelSim-Altera software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.
Perform the timing simulation in the ModelSim-Altera software.

Note: Refer to ModelSim software documentation to view and the interpret results of your simulation.

If you want to perform power analysis, proceed to perform power analysis with the PowerPlay Power Analyzer.