Compiling Libraries and Design Files with the ModelSim Software

If you have not already done so, set up a project with the ModelSim software.
On the Compile menu click Compile.
In the Library list of the Compile HDL Source Files dialog box, select the work library.
In the Files of Type list, select All Files (*.*), and in the Look in list, select the appropriate simulation model library.

Note: For VHDL-93 compliant designs, turn on Use 1993 Language Syntax under Default Options.

Click Compile.
Repeat steps 2 to 4 for the Verilog or VHDL Output File and the test bench file (if you are using one) that instantiates the Verilog or VHDL Output File.

Note:

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the txdigitalreset, rxanalogreset, and rxdigitalreset signals to start high. Assert txdigitalreset long enough so that it can be registered by tx_clkout and assert rxdigitalreset a few clock cycles longer than rxanalogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

Click Done.

If you have not already done so, perform set up a ModelSim project with command-line commands.

Note:

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the txdigitalreset, rxanalogreset, and rxdigitalreset signals to start high. Assert txdigitalreset long enough so that it can be registered by tx_clkout and assert rxdigitalreset a few clock cycles longer than rxanalogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

Enter the following commands to direct the ModelSim software to compile the appropriate libraries and design files for VHDL designs.

If your design contains the altgxb megafunction, type the following commands at the ModelSim prompt:

vlib lpm
vlib altera
vlib sgate
vmap lpm work
vmap altera work
vmap sgate work
vlib lpm<path to library>\220pack.vhd
vmap lpm lpm<path to library>\220model.vhd vcom -work sgate <path to library>\sgate_pack.vhd
vcom -work sgate<path to library>\sgate.vhd vcom -work stratixgx_gxb<path to library>\stratixgx_hssi_atoms.vhd.vhd vcom -work stratixgx_gxb<path to library>\stratixgx_hssi_components.vhd

To compile the device-specific simulation models, VHDL Output File, and test bench file (if you are using one), type the following commands at the ModelSim prompt:

vcom -work work<path to library>\altera_primitves.vhd (If your design targets a Stratix III or Cyclone III device.) vcom -work work<path to library>\altera_primitves_components.vhd (If your design targets a Stratix III or Cyclone III device.) vcom -work work<path to library>\<device family>_components.vhd vcom -work work<path to library>\<device family>_atoms.vhd vcom -work work<design name>.vho vcom -work work<test bench>.vhd

Note: For VHDL 93-compliant designs for APEX 20KE devices, type the following command to compile the simulation model:

vcom -93 -work work<path to library>\apex20ke_atoms.vhd

Enter the following commands to direct the ModelSim software to compile the appropriate libraries and design files for Verilog designs.

If your design contains the altgxb megafunction, type the following commands at the ModelSim prompt:

vlog -work work<path to library>\220model.v vlog -work work <path to library>\sgate.v

To compile the device-specific simulation models, Verilog Output File, and test bench file (if you are using one), type the following commands at the ModelSim prompt:

vlog -work work<path to library>/altera_primitives.v (If your design targets a Stratix III or Cyclone III device.) vlog -work work<path to library>/<device family>_atoms.v vlog -work work<design name>.vo
vlog -work work<test bench>.v