Performing a Functional Simulation with the ModelSim Software

You can run the Mentor Graphics ModelSim PE or SE software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components from the ModelSim interface or with command-line commands.

If you have not already done so, set up a project with the ModelSim software.
To map the design libraries to your work library:
1. On the File menu, point to New and click Library (File menu). The Create a New Library dialog box appears.
2. Type lpm in the Library Name box, type the name of the work library in the Library Maps to box, and then click OK.
3. Repeat steps 2a and 2b to map altera_mf to the work library.
If the Verilog HDL design contains CAM, RAM, or ROM functions, and you are using a Memory Initialization File (.mif), to convert memory initialization file for use with the ModelSim software:

Export the MIF File as a RAM Initialization File (.rif) in the Quartus II software.
Add parameter lpm_file = "<RIF name>.rif"; for the CAM, RAM, or ROM function to your top-level design or test bench file.
On the Compile menu, click Compile.
In the Compiler Options dialog box, click the Verilog tab.
Click Macro. In the Define Macro box, type USE_RIF. In the Value box, type 1.
Click OK to close the Define Macro box.
Click OK.

To compile the functional simulation libraries, Verilog or VHDL Design Files, and test bench files (if you are using a test bench):

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the txdigitalreset, rxanalogreset, and rxdigitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

1. On the Compile menu, click Compile.
2. In the Library list of the Compile HDL Source Files dialog box, select the work library.
3. In the File name list, type the directory path and file name of the functional simulation libraries.
  
  or
  
  In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog or VHDL Design File.
4. Click Compile.

Note: For VHDL designs that use the 220model.vhd library, turn on Use Explicit Declarations under Default Options in the Compile dialog box. For VHDL-93 compliant designs, turn on Use 1993 Language Syntax under Default Options.

1. Repeat steps 4b to 4d to compile the Verilog or VHDL Design File.
2. Repeat steps 4b to 4d to compile the test bench file(s).
3. Click Done.

To load the design:
1. On the Simulate menu, click Simulate. The Simulate dialog box appears.
2. In the Name list, click the + icon to expand the work directory.
3. Select the top-level design file to simulate.
4. Click Add.
5. Click Load.
Perform the functional simulation in the ModelSim software.

Note: You can use batch files to set up and compile each of the libraries automatically. Place all the commands displayed in the ModelSim-Altera or ModelSim PE or SE main window into a text file and name the file with a .do extension (that is, <file name>.do). Use this script to recompile the libraries if you update them.

To run a macro script:

From the Mentor Graphics ModelSim main window, chose Execute Macro.
In the Execute Do File dialog box, locate your ModelSim macro file (.do).
Click Open.

If you have not already done so, perform Setting Up a ModelSim Project with Command-Line Commands.
To compile the functional simulation libraries, VHDL or Verilog HDL design file, and optional test bench file, type the following commands at the ModelSim prompt:

Map to library work:

vlib lpm
vlib altera
vlib sgate
vmap lpm work
vmap altera work vmap sgate work

For VHDL-87compliant designs:

vcom -work work<path to library>\220pack.vhd vcom [-87] -explicit -work work<path to library>\220model_87.vhd vcom -work work<path to library>\altera_mf_components.vhd vcom [-87] -work work<path to library>\altera_mf_87.vhd vcom -work work<design name>.vhd vcom -work work<test bench>.vhd

For VHDL 93-compliant designs:

vcom -93 -work work<path to library>\220pack.vhd vcom -explicit -work work<path to library>\220model.vhd
vcom -work work<path to library>\altera_mf_components.vhd vcom -93 -work work<path to library>\altera_mf.vhd vcom -work work<design name>.vhd vcom -work work<test bench>.vhd

For Verilog HDL designs:

vlog -work work<path to library>\220model.v
vlog -work work<path to library>\altera_mf.v
vlog -work work<design name>.v vlog -work work<test bench>.v

Note: If the design contains the altgxb megafunction, you must also compile the stratixgx_mf functional simulation libraries.

Load the VHDL or Verilog HDL design file or test bench file for the design into the ModelSim software by typing one of the following commands at the command prompt:
vsim<work library>.<design name>

or

vsim<work library>.<top-level design entity>

Note: If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high. You must assert txdigitalreset and rxdigitalreset a few clock cycles longer than rxanalogreset.

Perform the functional simulation in the ModelSim software.