Start the NCSim software by typing nclaunch at a command prompt.
To create a work directory, on the Edit menu, point to Add, and then click New Library and type the name of the work library in the Library box.
Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:
When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software to perform a gate level simulation, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.
Edit the cds.lib and hdl.var files as follows:
File Name
File Contents
Function
cds.lib
DEFINE<work library>./work
Maps the <work library> to the physical location of the work library.
hdl.var
DEFINE WORK<work library>
Maps the NCSim variable WORK to the <work library>.
If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.
To elaborate the design, click Elaborator and type <work library>.<top-level entity name> in the Design Unit box.
To create a work library in the project directory, type the following command at the command prompt:
mkdir<work library>
Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:
When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.
Edit the cds.lib and hdl.var files as follows:
File Name
File Contents
Function
cds.lib
DEFINE<work library>./work
Maps the <work library> to the physical location of the work library.
hdl.var
DEFINE WORK<work library>
Maps the NCSim variable WORK to the <work library>.
Add the text parameter lpm_file = "<RIF name>.rif"; for the CAM, RAM, or ROM function to the top-level design or test bench file.
To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:
ncvlog<test bench file>
ncvlog<design name>.v
ncvlog/quartus/eda/sim_lib/220model.v
ncvlog/quartus/eda/sim_lib/altera_mf.v
ncvlog/quartus/eda/sim_lib/stratixgx_mf.v (If your design contains the altgxb megafunction)
Note:
If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.
Note: If you are using a RIF to specify memory initialization data, add the string -define NO_PLI before 220model.v and altera_mf.v in the above commands.
To elaborate and simulate the design, type the following command at the command prompt:
Start the NCSim software by typing nclaunch at a command prompt.
To create a work directory, on the Edit menu, point to Add, and then click New Library and type the name of the work library in the Library box.
Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:
When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.
Maps the <work library> to the physical location of the work library, and the variables LPM and ALTERA_MF to the work library.
hdl.var
DEFINE WORK<work library>
Maps the NCSim variable WORK to the <work library>.
Note: If you compile a design for the Arria GX or Stratix II GX device families that uses HSSI, the cds.lib must map multiple logical libraries to a physical library that you designate. The NC VHDL warning message "Multiple logical libraries mapped to a single location" might appear,however, you may ignore this warning since it does not affect simulation.Thecds.lib file must contain the following lines with <device family> replaced with either arriagx or stratixiigx as appropriate:
If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.
Note: For VHDL-93 compliant designs, turn on Enable VHDL 93 features in the VHDL Compiler dialog box.
To elaborate the design, click Elaborator and type <work library>.<top-level entity name> in the Design Unit box.
To simulate the design, click Simulator and type <work library>.<top-level entity name> in the Snapshot box.
To create a work library in the project directory, type the following command at the command prompt:
mkdir<work library>
Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:
When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.
Maps the <work library> to the physical location of the work library, and the variables LPM and ALTERA_MF to the work library.
hdl.var
DEFINE WORK<work library>
Maps the NCSim variable WORK to the <work library>.
Note: If you compile a design for the Arria GX or Stratix II GX device families that uses HSSI, the cds.lib must map multiple logical libraries to a physical library that you designate. The NC VHDL warning message "Multiple logical libraries mapped to a single location" might appear,however, you may ignore this warning since it does not affect simulation.Thecds.lib file must contain the following lines with <device family> replaced with either arriagx or stratixiigx as appropriate:
When defining library names, do not use library names that begin with numeric characters, for example, 220model.
To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:
ncvhdl /quartus/eda/sim_lib/altera_primitives.vhd (If your design targets a Stratix III or Cyclone III device.)
ncvhdl /quartus/eda/sim_lib/altera_primitives_components.vhd(If your design targets a Stratix III or Cyclone IIIdevice.)
ncvhdl -v93 -relax -work lpm<drive>:/quartus/eda/sim_lib/220pack.vhd
ncvhdl -v93 -relax -work lpm <drive>:/quartus/eda/sim_lib/220model.vhd
ncvhdl -v93 -work altera_mf<drive>:/quartus/eda/sim_lib/altera_mf.vhd
ncvhdl -v93 -work altera_mf<drive>:/quartus/eda/sim_lib/altera_mf_components.vhd
ncvhdl<test bench file>
ncvhdl<design name>.vhd
If your design contains the altgxb megafunction, type the following commands to compile the appropriate libraries:
If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.
Note: For the functional simulation libraries for VHDL-87 compliant designs, type the following commands to compile the simulation libraries:
文档资料
> 
To perform a functional simulation of a Verilog HDL design with the NCSim interface:
at a command prompt.
