Performing a Timing Simulation with the NCSim Software

Important: Altera recommends that you set Time scale settings to picoseconds (ps) in the interface or with command-line commands when performing timing simulations of designs with RAM.

The following sections demonstrate how perform a timing simulation of a Quartus II generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Cadence NCSim (NC-Verilog or NC-VHDL) software :

To perform a timing simulation of a Verilog HDL design with the NCSim interface:

If you have not already done so, perform Setting Up the NCSim Working Environment.
To generate the Verilog Output File:
1. Specify EDA tool settings in the Quartus II software.
2. Compile the design with the Quartus II software.

Note: The EDA Netlist Writer generates the Verilog Output File and the SDF Output File and places them in the /<project directory>/simulation/ncsim directory.

If you have already compiled the design, and want to specify different EDA tools settings and generate a Verilog Output File (.vo), VHDL Output File (.vho), and Standard Delay Format Output File (.sdo) without recompiling the design, you can use the Start EDA Netlist Writer command.

You can also use the Start EDA Netlist Writer command to generate script files to generate Value Change Dump File (.vcd) in EDA simulation tools.

Copy the cds.lib and hdl.var files, located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.

Edit the cds.lib and hdl.var files as follows:

File Name	File Contents	Function
cds.lib	`DEFINE`<work library>`./work`	Maps the <work library> to the physical location of the work library.
hdl.var	`DEFINE WORK`<work library>	Maps the NCSim variable WORK to the <work library>.

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

Start the NCSim software by typing nclaunch at a command prompt.

Note: When you run the NCSim software automatically after compilation in the Quartus II software, the NCSim software automatically performs steps 5 through 7.

To create a work library on the Edit menu, point to Add, and then click New Library. Type the name of the work library in the Library box.

Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:

When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.

To compile the appropriate project files and libraries into the work library:
1. Click Verilog Compiler.
2. In the File box, type the path of the test bench file (if you are using one).
3. In the Work Library list, select the work library.
4. Click OK.
5. Repeat steps 7a to 7d to compile the Verilog Output File for the project and the appropriate post-fit libraries.
To elaborate the design, click Elaborator and type <work library>.<top-level entity name> in the Design Unit box.
To simulate the design, click Simulator and type <work library>.<top-level entity name> in the Design Unit box.
To direct the NCSim software to generate a Value Change Dump File that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer:
1. In the file explorer pane, select the <test bench or design instance name>_dump_all_vcd_nodes.tclTcl Script File (.tcl) generated by the Quartus II EDA Netlist Writer.
2. On the File menu, click Source. The Tcl Script File directs the NCSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.

To perform a timing simulation of a Verilog HDL design with command-line commands:

If you have not already done so, perform Setting Up the NCSim Working Environment.
To generate the Verilog Output File:
1. Specify EDA tool settings in the Quartus II software.
2. Compile the design with the Quartus II software.

Note: The EDA Netlist Writer generates the Verilog Output File and the SDF Output File and places them in the output directory specified. The default location is /<project directory>/simulation/ncsim.

You can also use the Start EDA Netlist Writer command to generate script files to generate Value Change Dump File (.vcd) in EDA simulation tools.

To create a work library in the project directory, type the following command at the command prompt: mkdir<work library>

Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:

When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation..

Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.

Note: When you run the NCSim software automatically after compilation in the Quartus II software, the NCSim software automatically performs steps 4 and 5.

Edit the cds.lib and hdl.var files as follows:

File Name	File Contents	Function
cds.lib	`DEFINE`<work library>`./work`	Maps the <work library> to the physical location of the work library.
hdl.var	`DEFINE WORK`<work library>	Maps the NCSim variable WORK to the <work library>.

You can type the following commands at the command prompt from within the project directory to compile the appropriate project files and libraries into the work library.

If the design contains the altgxb megafunction, compile the altgxb libraries by typing the following commands at a command prompt:

ncvlog /quartus/eda/sim_lib/220model.v ncvlog /quartus/eda/sim_lib/sgate.v ncvlog /quartus/eda/sim_lib/stratixgx_hssi_atoms.v

Compile the Verilog Output File, test bench file (if you are using one), and the appropriate timing simulation library by typing the following commands at a command prompt:

ncvlog /quartus/eda/sim_lib/altera_primitives.v (If your design targets a Stratix III or Cyclone III device.) ncvlog /quartus/eda/sim_lib/ <device family>_atoms.v ncvlog <test bench file>.v ncvlog <project name>.vo

Note: If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.

To simulate high-speed circuits, including designs that use HSSI, LVDS, and PLLs, type the following command at the command prompt to enable transport delays:

ncelab -pulse_e 0 -pulse_r 0 -timescale "1ps/1ps" work.<top-level entity name>

Note: For more information about transport and inertial delays, please refer to the NCSIM User Guide.

To elaborate and simulate the design, type the following commands at the command prompt:

ncsim<work library>.<top-level entity name>

To direct the NCSim software to generate a Value Change Dump File that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer:
1. In the file explorer pane, select the <test bench or design instance name>_dump_all_vcd_nodes.tclTcl Script File (.tcl) generated by the Quartus II EDA Netlist Writer.
2. On the File menu, click Source. The Tcl Script File directs the NCSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.

To perform a timing simulation of a VHDL design with the NCSim interface:

If you have not already done so, perform Setting Up the NCSim Working Environment.
To generate the VHDL Output File (.vho):
1. Specify EDA tool settings in the Quartus II software.
2. Compile the design with the Quartus II software.

Note: The EDA Netlist Writer generates the VHDL Output File and the SDF Output File and places it in the output directory specified. The default location is /<project directory>/simulation/ncsim.

You can also use the Start EDA Netlist Writer command to generate script files to generate Value Change Dump File (.vcd) in EDA simulation tools.

Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.

Note: If you compile a design for the Arria GX or Stratix II GX device families that uses HSSI, the cds.lib must map multiple logical libraries to a physical library that you designate. The NC VHDL warning message "Multiple logical libraries mapped to a single location" might appear,however, you may ignore this warning since it does not affect simulation.The cds.lib file must contain the following lines with <device family> replaced with either arriagx or stratixiigx as appropriate:

SOFTINCLUDE ${CDS_INST_DIR}/tools/inca/files/cdsvhdl.lib

SOFTINCLUDE ${CDS_INST_DIR}/tools/inca/files/cdsvlog.lib

DEFINE work ./<physical library name>

DEFINE <device family>_hssi ./<physical library name>

DEFINE <device family> ./<physical library name>

DEFINE lpm ./<physical library name>

DEFINE sgate ./<physical library name>

To map the <device family> variable to a device-specific directory and to map the work library to the physical location of the work library, add the following lines to the cds.lib file:

DEFINE<device family>./<device family>DEFINE<work library>./work

Create a work library in the project directory by typing mkdir<work library> at a command prompt.

Note: When you run the NCSim software automatically after compilation in the Quartus II software, the NCSim software automatically performs steps 4 through 7.

To start the NCSim software, type nclaunch at the command prompt:

To create a work library, on the Edit menu, point to Add , and then click New Library. Type the name of the work library in the Library box.

Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:

When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.

To compile the appropriate project files and simulation libraries into the work library:

1. Click VHDL Compiler.
2. In the File box, type the path of the test bench file (if you are using one).
3. In the Work Library list, select the work library.
4. Click OK.
5. Repeat steps 8a to 8d to compile the VHDL Output File for the project and the appropriate post-fit libraries.

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

Note: For VHDL-93 compliant designs, turn on Enable VHDL 93 features in the VHDL Compiler dialog box.

To compile the Standard Delay Output File:
1. Click SDF Compiler.
2. In the SDF File box, specify the name of the Standard Delay Output File for the project.
3. Make sure <project name>.sdf.X appears in the Output file name box.
4. Click OK.
To elaborate the design, click Elaborator and type <work library>.<top-level entity name> in the Design Unit box.
To simulate the design, click Simulator and type <work library>.<top-level entity name> in the Snapshot box.
To direct the NCSim software to generate a Value Change Dump File that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer:
1. In the file explorer pane, select the <test bench or design instance name>_dump_all_vcd_nodes.tclTcl Script File (.tcl) generated by the Quartus II EDA Netlist Writer.
2. On the File menu, click Source. The Tcl Script File directs the NCSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.

To perform a timing simulation of a VHDL design with command-line commands:

If you have not already done so, perform Setting Up the NCSim Working Environment.
To generate the VHDL Output File (.vho):
1. Specify EDA tool settings in the Quartus II software.
2. Compile the design with the Quartus II software.

Note: The EDA Netlist Writer generates the VHDL Output File and the SDF Output File and places them in the output directory specified, the default location is /<project directory>/simulation/ncsim.

You can also use the Start EDA Netlist Writer command to generate script files to generate Value Change Dump File (.vcd) in EDA simulation tools.

To create a work library in the project directory, type the following command at the command prompt:

mkdir<work library>

Note: Altera recommends using the NCSim (NC-Verilog or NC-VHDL) default library names when you create a library. You should name the NCSim software libraries as follows:

When you run the NCSim software independently from the Quartus II software, you should name your library work.
When you run the NCSim software automatically from the Quartus II software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.

Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.

SOFTINCLUDE ${CDS_INST_DIR}/tools/inca/files/cdsvhdl.lib

SOFTINCLUDE ${CDS_INST_DIR}/tools/inca/files/cdsvlog.lib

DEFINE work ./<physical library name>

DEFINE <device family>_hssi ./<physical library name>

DEFINE <device family> ./<physical library name>

DEFINE lpm ./<physical library name>

DEFINE sgate ./<physical library name>

To map the <device family> variable to a device-specific directory and to map the work library to the physical location of the work library, add the following lines to the cds.lib file:

DEFINE<device family>./<device family>DEFINE<work library>./work

Note: When you run the NCSim software automatically after compilation in the Quartus II software, the NCSim software automatically performs steps 4 and 5.
To annotate the timing data in the SDF Output File:
1. Compile the SDF Output File using the ncsdfc utility by typing the following command at the command prompt:
  
  ncsdfc<project name>_vhd.sdo
  
  The ncsdfc utility generates a <project name>.sdf.X compiled SDF Output File and places it in the /<project directory>/simulation/ncsim directory.
2. Specify the compiled SDF Output File for the project by adding the following line to the SDF command file for the project:
  
  COMPILED_SDF_FILE = "<project name>.sdf.X
3. Specify the scope level by adding the following line to the SDF command file:
  
  SCOPE = :<instance name or lower-level entity being annotated for timing>
To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:

If your design contains the altgxb megafunction, compile the altgxb libraries by typing the following commands at a command prompt:

vhdlan /quartus/eda/sim_lib/220pack.vhd vhdlan /quartus/eda/sim_lib/220model.vhd vhdlan /quartus/eda/sim_lib/sgate_pack.vhd vhdlan /quartus/eda/sim_lib/sgate.vhd vhdlan /quartus/eda/sim_lib/stratixgx_hssi_atoms.vhd vhdlan /quartus/eda/sim_lib/stratixgx_hssi_components.vhd

To compile the VHDL Output File, test bench file (if you are using one), and the appropriate timing simulation libraries, type the following commands at a command prompt:

ncvhdl /quartus/eda/sim_lib/altera_primitives.vhd (If your design targets a Stratix III or Cyclone III device.) ncvhdl /quartus/eda/sim_lib/altera_primitives_components.vhd (If your design targets a Stratix III or Cyclone III device.) ncvhdl -v93 -work<device family>/quartus/eda/sim_lib/<device family>_atoms.vhd ncvhdl -v93 -work<device family> /quartus/eda/sim_lib/<device family>_components.vhd ncvhdl<test bench file>.vhd ncvhdl<project name>.vho

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that tx_clkout registers it and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that rx_clkout can register rx_digitalreset. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

Note: For VHDL-87 compliant designs for APEX 20KE devices, type the following command to compile the simulation model library instead:

ncvhdl [-v87] -work<device family>/quartus/eda/sim_lib/apex20ke_atoms_87.vhd

To simulate high-speed circuits, including designs that use HSSI, LVDS, and PLLs, type the following command at the command prompt to enable transport delays:

ncelab -pulse_e 0 -pulse_r 0 -timescale "1ps/1ps" work.<top-level entity name>

Note: For more information about transport and inertial delays, please refer to the NCSIM User Guide.

To elaborate and simulate the design, type the following commands at the command prompt:
ncelab -sdf_cmd_file<SDF command file name><work library>.<top-level entity name> ncsim<work library>.<top-level entity name>

To direct the NCSim software to generate a Value Change Dump File that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer:
1. In the file explorer pane, select the <test bench or design instance name>_dump_all_vcd_nodes.tclTcl Script File (.tcl) generated by the Quartus II EDA Netlist Writer.
2. On the File menu, click Source. The Tcl Script File directs the NCSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.

If you want to perform power analysis, perform power analysis with the PowerPlay Power Analyzer.