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主页 > 支持 > 软件 > 仿真工具 > Performing a Functional Simulation with the VCS Software 打印此页 发送此页 Performing a Functional Simulation with the VCS Software To prepare for a functional simulation of a Verilog HDL design with the Synopsys VCS software, you can type a command that compiles the design and generates a simv.exe file that you can use to simulate the design. Alternatively, you can type a command that compiles and simulates the design automatically. To perform a functional simulation of a Verilog HDL design with the VCS software from the command line: If you have not already done so, set up the VCS working environment. If the Verilog HDL design uses memory initialization data in a Hexadecimal (Intel-Format) File (.hex) or a Memory Initialization File (.mif) for the INIT_FILE parameter, to convert the initial memory contents for use with the VCS software: Export the Hexadecimal (Intel-Format) File or Memory Initialization File as a RAM Initialization File (.rif). Add parameter lpm_file = "<Ram Initialization File name>"; to the Verilog design file or test bench file. Refer to the following table and type the appropriate command at the command prompt.   Design Type Commands for Compiling the Design and Generating a simv.exe File Commands for Compiling and then Automatically Simulating the Design Verilog design without HEX File vcs <design name>.v [<test bench>.v] -v <library file>.v  vcs -R <design name>.v [<test bench>.v] -v <library file>.v  Verilog design with HEX File vcs -v \quartus\eda\sim_lib\nopli.v <library file>.v <design name>.v [<test bench>.v] -  vcs -R -v \quartus\eda\sim_lib\nopli.v <library file>.v <design name>.v [<test bench>.v] -    You must type the above commands for each source file in the design, where the <design name>.v and <test bench>.v variables may each represent one or more of the source files of the design. The <library file>.v variable may represent one or more of the functional simulation libraries. Refer to the VCS User Guide for more information on the required and optional environment variables.   Note: If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high. If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the txdigitalreset, rxanalogreset, and rxdigitalreset signals to start high. Assert txdigitalreset long enough so that it can be registered by tx_clkout and assert rxdigitalreset a few clock cycles longer than rxanalogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.   To continue with the VCS simulation flow, proceed to Performing a Timing Simulation with the VCS Software.     给本页评分

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