Performing a Timing Simulation with the VCS Software

To perform a timing simulation of a Quartus II–generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Synopsys VCS software:

1. If you have not already done so, perform Setting Up the VCS Working Environment.

2. To generate the Verilog Output File:

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

3. To direct the VCS software to generate a Value Change Dump File (.vcd) that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer, include the Quartus II-generated Verilog Design File (.v) in the test bench file for the design by adding the following line to the test bench file:

   include <test bench or design instance name>_dump_all_vcd_nodes.v

   The Verilog Design File directs the VCS software to monitor and write the output signals contained in the Verilog Design File to a VCD File during simulation.

4. You can compile the Verilog Output File with the VCS software with one of the following commands typed at the command prompt.

To generate a simv.exe file, which you can use later to simulate the design:

vcs <test bench>.v <design name>.vo -v \quartus\eda\sim_lib\altera_primitives.v +compsdf  (If your design targets a Stratix III or Cyclone III device.)
vcs <test bench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf 

3. or

4. To compile the Verilog Output File with the VCS software and simulate it automatically:

5. vcs <test bench>.v <design name>.vo -v \quartus\eda\sim_lib\altera_primitives.v +compsdf  (If your design targets a Stratix III or Cyclone III device.)
vcs -R <test bench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf 

    

   Important: If your design contains the altgxb megafunction or the alt2gxb megafunction, please refer to the appropriate megafunction topic for required settings information.