Performing a Functional Simulation with the VCS MX Software

You can use the Synopsys VCS MX software to perform an RTL-level functional simulation of a Verilog HDL or VHDL design that contains Altera-specific components:

If you have not already done so, perform Setting Up the VCS MX Working Environment.
Create a .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VCS MX software to use the functional simulation libraries during simulation:

WORK ><work library>220model ><work library>altera_mf ><work library>sgate ><work library>altgxb ><work library>
<work library> : <physical path to work library>
In the VCS MX shell, point the environment variable SYNOPSYS_SIM_SETUP to the .synopsys_vss.setup file.
To create a work library in the project directory, type the following command at a command prompt:
mkdir<work library>

Note: Altera recommends using the Synopsys VCS MX default library names when you create a library. You should name the VCS MX software libraries as follows:

When you run the VCS MX software independently from the Quartus II software, you should name your library work.
When you run the VCS MX software automatically from the Quartus II software, the work library is named rtl_work for a RTL simulation or gate_work for a Gate-Level simulation. The library work is mapped to either rtl_work or gate_work.

To compile the Verilog Design Files (.v), test bench file (if you are using one) and Altera prerouting simulation libraries, type the following commands at a command prompt:

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that it can be registered by tx_clkout and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

vlogan/usr/quartus/eda/sim_lib/220model.v vlogan /usr/quartus/eda/sim_lib/altera_mf.v vlogan <design name>.v vlogan <test bench file>.v

If your design contains the altgxb megafunction, type the following commands to compile the appropriate libraries:

vlogan/usr/quartus/eda/sim_lib/sgate.v vlogan/usr/quartus/eda/sim_lib/stratixgx_mf.v

1. To start a simulation session by elaborating and compiling and to create the simv executable to simulate the design, type the following command at the command prompt:
  
  v<top-level entity>
2. To simulate the design, type the following command at a command prompt:
3. simv
1. To perform the simulation interactively, type simv -i at the command prompt.

If you have not already done so, perform Setting Up the VCS MX Working Environment.
Create a .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VCS MX software to use the functional simulation libraries during simulation:

WORK ><work library>220model ><work library>altera_mf ><work library>sgate ><work library>altgxb ><work library>
<work library> : <physical path to work library>
In the VCS MX shell, point the environment variable SYNOPSYS_SIM_SETUP to the .synopsys_vss.setup file.
To create a work library in the project directory, type the following command at a command prompt:
mkdir<work library>

Note: Altera recommends using the Synopsys VCS MX default library names when you create a library. You should name the VCS MX software libraries as follows:

When you run the VCS MX software independently from the Quartus II software, you should name your library work.
When you run the VCS MX software automatically from the Quartus II software, the work library is named rtl_work for a RTL simulation or gate_work for a Gate-Level simulation. The library work is mapped to either rtl_work or gate_work.

To compile the VHDL Design File (.vhd), test bench file (if you are using one) and Altera prerouting simulation libraries, type the following commands at a command prompt:

Note:

If the design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rx_analogreset and rx_digitalreset signals to start high.
If your design contains the alt2gxb megafunction, Altera recommends that you set the value of the gxb_powerdown signal to start high in the test bench or waveform file for the design. If the instantiated alt2gxb megafunction does not use gxb_powerdown signal, Altera requires that you set the values of the tx_digitalreset, rx_analogreset, and rx_digitalreset signals to start high. Assert tx_digitalreset long enough so that it can be registered by tx_clkout and assert rx_digitalreset a few clock cycles longer than rx_analogreset so that it can be registered by rx_clkout. Altera requires that you apply the same reset sequence mentioned above after dynamic channel reconfiguration.

vhdlan/usr/quartus/eda/sim_lib/220pack.vhd vhdlan/usr/quartus/eda/sim_lib/220model.vhd vhdlan /usr/quartus/eda/sim_lib/altera_mf.vhd vhdlan /usr/quartus/eda/sim_lib/altera_mf_components.vhd vhdlan <design name>.vhd
vhdlan <test bench file>.vhd

If your design contains the altgxb megafunction, type the following commands to compile the appropriate libraries:

vhdlan/usr/quartus/eda/sim_lib/sgate_pack.vhd vhdlan/usr/quartus/eda/sim_lib/sgate.vhd vhdlan/usr/quartus/eda/sim_lib/stratixgx_mf.vhd vhdlan/usr/quartus/eda/sim_lib/stratixgx_mf_components.vhd

Note: For VHDL 87-compliant designs, type the following commands to compile the VHDL-87 compliant simulation model libraries:

vhdlan -vhdl87 /usr/quartus/eda/sim_lib/220model_87.vhd vhdlan-vhdl87 /usr/quartus/eda/sim_lib/altera_mf_87.vhd

1. To start a simulation session by elaborating and compiling and to create the scsim executable to simulate the design, type the following command at the command prompt:
  
  scs<top-level entity>
2. To simulate the design, type the following command at a command prompt:
3. scsim -xlrm<work library>.<top-level entity>
1. To perform the simulation interactively, type scsim -i at the command prompt.