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Perform a Functional Simulation with the VSS Software

To use the Synopsys VHDL System Simulator (VSS) software to perform a functional simulation of a VHDL design that contains Altera-specific components:

  1. If you have not already done so, perform 1. Set Up the VSS Working Environment.

  2. Add the following lines to your .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VSS software to use the functional simulation libraries during simulation:

    WORK > <work library>
    220model >
    <work library>
    altera_mf >
    <work library>
    <work library>
    > <physical path to work library>

     

    NOTE

    Add the altera variable if you wish to simulate the architecture control logic functions in the alt_mf library, located at /usr/quartus/eda/synopsys/library/alt_mf/lib.

     

  3. Create a work library in the project directory by typing the following command at a command prompt:  More Details

  4. mkdir <work library> Enter

  1. To compile the VHDL Design File (.vhd), test bench file (if you are using one) and Altera prerouting simulation libraries, type the following commands at a command prompt:

  2. vhdlan <test bench file> Enter
    vhdlan
    <design name>.vhd Enter
    vhdlan
    /usr/quartus/eda/sim_lib/220model.vhd Enter
    vhdlan
    /usr/quartus/eda/sim_lib/altera_mf.vhd Enter

     

    NOTE

    For VHDL 87-compliant designs, type the following commands to compile the VHDL-87 compliant simulation model libraries:

    vhdlan -vhdl87 /usr/quartus/eda/sim_lib/220model_87.vhd Enter
    vhdlan
    -vhdl87 /usr/quartus/eda/sim_lib/altera_mf_87.vhd Enter

     

  1. To simulate the design, type the following command at a command prompt (where <VHDL configuration name> represents the configuration name in the test bench file):

  2. scsim <work library>.<VHDL configuration name> Enter

     

    Note:

    1. The VSS software requires each architecture or entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis.

    2. Refer to the VHDL System Simulator Core Programs Manual for more information about the VSS software.

     

  1. To continue with the VSS simulation flow, proceed to 3. Perform a Timing Simulation with the VSS Software.

 

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