Primitive and Old-Style Macrofunction Instantiation Example for Verilog HDL
You can instantiate the Quartus II primitives listed in Design Compiler Technology Libraries in Verilog HDL designs. These primitives can be used to control synthesis in the Quartus II software. You can also instantiate Quartus II megafunctions and old-style macrofunctions.
Unlike other logic functions, Quartus II primitives do not need to be defined with hollow-body functions unless you wish to simulate the design with with any supported simulation software. Any references to these primitives are resolved by the Synopsys compilers. All buffer primitives except the ATRIBUF and TRIBUF primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."
The 4-bit full adder code sample contains registered output that also instantiates an AGLOBAL or GLOBAL primitive. The design uses an old-style 7483 macrofunction, which is represented as a hollow body named fa4.
4-Bit Adder Design with Registered Output (adder.v)
// module declaration for GLOBAL primitive
module GLOBAL (A_OUT, A_IN);
input A_IN;
output A_OUT;
endmodule
You can analyze the 4-bit adder design with the Synopsys HDL Compiler for Verilog software. The hollow-body description of the fa4 function is required. It contains port declarations and does not include any information about the design's function or operation. However, the hollow-body description can be in the design file, as shown in Figure 1, or in a separate file, as shown in Figure 2.
If the hollow-body description is in a separate file, you must analyze it before analyzing the higher-level function with the HDL Compiler for Verilog to produce a hollow-body component. This component contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.
You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the Quartus II software. After the HDL Compiler for Verilog software successfully processes the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.
Synthesized Design Generated by the Design Compiler
However, before you compile the EDIF netlist file with the Quartus II software, you must create the adder.lmf file, shown in Figure 4, to map the fa4 function to the equivalent Quartus II function (7483). You must then specify the Library Mapping File (.lmf) as LMF #2 in the Design Entry and Synthesis page of the Settings dialog box.
Library Mapping File Excerpt for fa4
BEGIN
FUNCTION 7483 (c0, a1, b1, a2, b2, a3, b3, a4, b4,)
RETURNS (s1, s2, s3, s4, c4)
FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
"b3","a4", "b4")
RETURNS ("s1", "s2", "s3", "s4", "c4")
END
When you compile the design with the Quartus II software, you can disregard the warning "EDIF cell<name>already has LMF mapping so CONTENTS construct has been ignored". To verify the global Clock and global Reset usage, as well as the number of logic cells used, refer to the adder.rpt Report File generated by the Quartus II software.
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