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主页 > 支持 > 软件 > 综合工具 > Design Compiler > Architecture Control Logic Function Instantiation Example for VHDL 打印此页 发送此页 Architecture Control Logic Function Instantiation Example for VHDL You can instantiate Altera-provided logic functions from the alt_mf library, which includes the a_8fadd, a_8mcomp, a_8count, and a_81mux functions, in VHDL designs. Altera provides behavioral descriptions of these functions that support pre-routing simulation of your top-level design with any supported simulation software. When you instantiate one of these functions, you can either include a Component Declaration for the function, or use the Altera-provided shell script analyze_vss to create a design library called altera so that you can reference the functions through the VHDL Library and Use Clauses. The VHDL Library and Use Clauses direct the Design Compiler to incorporate the library files when it compiles your top-level design file. The following example shows an 8-bit counter that is instantiated using the a_8count function. Sample VHDL File with Logic Function Instantiation LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.quartus.ALL; ENTITY counter IS PORT (clock,ena,load,dnup,set,clear : IN STD_LOGIC; i : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cout : OUT STD_LOGIC); END counter; ARCHITECTURE structure OF counter IS BEGIN u1 : a_8count PORT MAP (a=>i(0), b=>i(1), c=>i(2), d=>i(3), e=>i(4), f=>i(5), g=>i(6), h=>i(7), ldn=>load, gn=>ena, dnup=>dnup, setn=>set, clrn=>clear, clk=>clock, qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3), qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7), cout=>cout); END structure; CONFIGURATION conf OF counter IS FOR structure END FOR; END conf;     给本页评分

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