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主页 > 支持 > 软件 > 综合工具 > Design Compiler > Setting Up the Design Compiler Working Environment 打印此页 发送此页 Setting Up the Design Compiler Working Environment To use the Quartus II software with Synopsys software, you must first install the Quartus II software, then establish an environment that facilitates entering and processing designs by modifying your Synopsys configuration files. The Quartus II/Synopsys interface is installed automatically when you install the Quartus II software on your workstation. To set up the Design Compiler working environment: Make sure you have the following versions of the Quartus II software and the Design Compiler software: The following software applications are used to generate, process, synthesize, and verify a project with the Quartus II and Synopsys software:   Synopsys Altera Design Compiler version 2004.12-SP4 Quartus II version 7.2   This version of the Design Compiler software supports all Altera devices supported by the Quartus II software. Compilation with the Synopsys Design Compiler is available only on Sun SPARC stations running Solaris 2.4 or higher.   Note: The Quartus II Software Release Notes are available on the Altera website and provide up-to-date information on which versions of Synopsys applications the current version of the Quartus II software supports. The Quartus II readme.txt file provides information on installation and operating requirements. You should read the Release Notes and readme.txt file before installing the Quartus II software. After installation, you can open the Release Notes and readme.txt file from the Quartus II Help menu.   Make sure the appropriate Quartus II/Synopsys interface directories are installed. The following table shows the Quartus II/Synopsys interface subdirectories that are created in the Quartus II system directory (by default, the /usr/quartus directory) during the Quartus II software installation.   Directory Description ./eda/synopsys/bin Contains script programs to analyze Synopsys DesignWare models and Altera-provided macrofunctions. ./eda/synopsys/examples Contains sample files. ./eda/synopsys/sim/verilog/altera Contains the Verilog HDL functional simulation library for Verilog HDL projects. ./eda/synopsys/sim/vhdl/vital Contains the VITAL 95 simulation library. You use this library when you perform functional simulation of the design before compiling it with the Quartus II software. ./eda/synopsys/mf Contains behavioral VHDL models of some currently supported Altera macrofunctions, along with their component declarations: a_81mux a_8count a_8fadd a_8mcomp Libraries in this directory allow you to instantiate, synthesize, and simulate these macrofunctions. ./eda/sim_lib Contains the post-fit library for simulation.   Note: The information presented here assumes that you are using C shell and that your Quartus II system directory is /usr/quartus. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. For information on the other directories that are created during the Quartus II software installation, see "Quartus II File Organization" in the Quartus II Installation & Licensing for PCs or Quartus II Installation & Licensing for UNIX and Linux workstations manuals. To set up your .synopsys_dc.setup configuration file: Add the following lines to your .synopsys_dc.setup configuration file. The following example shows an excerpt from a sample file. search_path = {./usr/quartus/synopsys/dc/syn/<device family>/lib}; target_library = {<technology library>}; symbol_library = {altera.sdb}; link_library = {<technology library>}; edifout_netlist_only = "true"; edifout_power_and_ground_representation = "net"; edifout_power_net_name = "VDD"; edifout_ground_net_name = "GND"; edifout_no_array = "false"; edifin_power_net_name = "VDD"; edifin_ground_net_name = "GND"; compile_fix_multiple_port_nets = "true" bus_naming_style = "%s<%d>"; bus_dimension_separator_style = "><"; bus_inference_style = "%s<%d>"; Specify one of the Design Compiler technology libraries for the target_library and link_library parameters in the .synopsys_dc.setup file. If you plan to instantiate architecture control logic functions from the alt_mf library, add the following line to your .synopsys_dc.setup file: define_design_lib altera -path /usr/quartus/eda/synopsys/mf/src  Specify the device family for the <device family> variable in the search_path parameter. Important: The .synopsys_dc.setup configuration file allows you to set Synopsys Design Compiler variables. The compilers read .synopsys_dc.setup files from three directories, in the following order: The Synopsys root directory Your home directory The Design Compiler system directory   The most recently read configuration file has highest priority. For example, a configuration file Design Compiler in the system directory has priority over the other configuration files, and a configuration file in the home directory has priority over a configuration file in the root directory. Add the /usr/quartus/bin directory to the PATH environment variable in your .cshrc file in order to run the Quartus II software. Source your .cshrc file by typing source .cshrc at the UNIX prompt. To continue with the Design Compiler design flow with the DesignWare interface, set Up the DesignWare interface. Otherwise create a design for use with the Design Compiler software.     给本页评分

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