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主页 > 支持 > 软件 > 综合工具 > Design Compiler > Altera/DesignWare Synthetic Libraries 打印此页 发送此页 Altera/DesignWare Synthetic Libraries The Altera/Synopsys DesignWare interface provides accurate area and timing prediction for designs that have been synthesized by the Synopsys design tools and targeted for ACEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Cyclone, Cyclone II, Cyclone III, FLEX 6000, FLEX 10K, HardCopy II, MAX II, Mercury, Stratix, Stratix II, Stratix II GX, Stratix III, and Stratix GX devices. The DesignWare interface also ensures that the area and timing information closely matches the final device implementation generated by the Quartus II software. The DesignWare interface synthesizes designs by operator inference. This interface supports bus widths of up to 32 bits, except adder functions, which support bus widths of up to 64 bits. The Altera/DesignWare interface offers three major advantages to Synopsys designers: Automatic access to carry and cascade chain functions Optimal routing of designs Improved area and performance prediction capability in Synopsys tools The following table lists the Altera DesignWare synthetic libraries.   Altera Device Family Synopsys Design Compiler ACEX 1K synthetic library acex1k.sldb APEX 20K synthetic library apex20k-3.sldb APEX 20KC synthetic library apex20kc-3.sldb APEX 20KE synthetic library apex20ke-3.sldb APEX II synthetic library apexii-3.sldb Arria GX synthetic library arriagx.sldb Cyclone synthetic library cyclone.sldb Cyclone II synthetic library cycloneii.sldb Cyclone III synthetic library cycloneiii.sldb FLEX 6000 synthetic library flex6000-2.sldb flex6000-3.sldb FLEX 10K synthetic library flex10ke-3.sldb HardCopy II synthetic library hardcopyii.sldb MAX II synthetic library maxii-3.sldb Mercury synthetic library mercury-3.sldb Stratix synthetic library stratix-3.sldb Stratix GX synthetic library stratixgx.sldb Stratix II synthetic library stratixii.sldb Stratix II GX synthetic library stratixiigx.sldb Stratix III synthetic library stratixiii.sldb   The following table lists functions included in the DesignWare synthetic libraries.   Name Function flex_add Sum of A, B, and Carry-In flex_carry Carry of A, B, and Carry-In flex_sub Difference of A, B, and Borrow-In flex_borrow Borrow of A, B, and Borrow-In flex_gt, flex_sgt Greater than (flex_gt is unsigned; flex_sgt is signed) flex_carry_gt Greater than Carry flex_lt, flex_slt Less than (flex_lt is unsigned; flex_slt is signed) flex_carry_lt Less than Carry flex_gteq, flex_sgteq Greater than or equal to (flex_gteq is unsigned; flex_sgteq is signed) flex_carry_gteq Greater than or equal to Carry flex_inc Incrementer (Count = Count + 1) flex_carry_inc Incrementer Carry (Count = Count + 1) flex_dec Decrementer (Count = Count - 1) flex_carry_dec Decrementer Carry (Count = Count - 1) flex_lteq, flex_slteq Less than or equal to (flex_lteq is unsigned; flex_slteq is signed) flex_carry_lteq Less than or equal to Carry flex_count Counter aflex_carry_count Counter Carry flex_add_sub Adder/Subtractor flex_inc_dec Incrementer/Decrementer flex_umult, flex_smult Multiplier (flex_umult is unsigned; flex_smult is signed)   Refer to the Synopsys DesignWare Databook and VHDL Compiler Reference Manual for related information.     给本页评分

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