Altera VHDL and Verilog HDL alt_mf Logic Function Library (Design Compiler Software)
The alt_mf library contains behavioral VHDL and Verilog HDL models of the Altera-provided architecture control logic functions shown in the following table. You can simulate VHDL Design Files (.vhd) and Verilog Design Files (.v) that instantiate these functions with a supported simulator, both before and after being compiled with the Synopsys Design Compiler software.
Name
Description
a_8fadd
8-bit full adder
a_8mcomp
8-bit magnitude comparator
a_8count
8-bit up/down counter
a_81mux
8-to-1 multiplexer
The behavioral descriptions of these four functions are contained in the /usr/quartus/eda/synopsys/mf/src directory. The table below lists the files contained in this directory.
File
Description
mf.vhd
Contains behavioral VHDL descriptions of the logic functions.
mf_components.vhd
Contains VHDL Component Declarations for the logic functions.
mf.v
Contains behavioral Verilog HDL descriptions of the logic functions.
If you wish to simulate a VHDL design containing these logic functions, you can use the Altera-provided shell script /usr/quartus/eda/synopsys/bin/alt_mf.sh to create a design library called altera. This library allows you to reference the functions through the VHDL Library and Use Clauses, which direct the Design Compiler software to incorporate the library files when it compiles your top-level design file. The alt_mf.sh shell script creates the altera design library by analyzing the simulation models in the /usr/quartus/eda/synopsys/mf/src directory.
Note: The information presented here assumes that you are using C shell and that your Quartus II system directory is /usr/quartus. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.
Complete VHDL and Verilog HDL behavioral descriptions of these logic functions are included in the mf.vhd and mf.v files so that you can optionally retarget your design to other technology libraries.
文档资料
> 
