The Altera-provided Synopsys Design Compiler technology libraries contain primitives that the Synopsys compilers use to map designs to the target device architecture. These primitives contain timing and area information that the Synopsys compilers use to meet area and performance requirements. Altera recommends instantiating these functions directly in designs only if the Synopsys compilers do not appear to recognize the functions when synthesizing a design, or if you prefer to manually optimize certain portions of the design. The following table shows the functions provided in these libraries.
Name
Note (1)
Description
Name
Description
LCELL
Logic cell buffer primitive
TRIBUF
Note (2)
Tri-state buffer primitive
GLOBAL
Global input buffer primitive
SOFT
Soft buffer primitive
CASCADE
Cascade buffer primitive
OPNDRN
Open-drain buffer primitive
CARRY
Carry buffer primitive
DFF
DFFE
DFFS
Note (3)
D-type flipflop with Clock Enable primitive
LATCH
Latch primitive
TFF
TFFE
TFFS
Note (3)
T-type flipflop primitive
Notes:
1) All buffer primitive names except OPNDRN must be prefixed with an "A" in APEX 20K designs
2) The TRIBUF primitive is equivalent to the TRI primitive in the Quartus II software.
3) The DFFE and TFFE primitives include a clock enable input; the DFFS and TFFS primitives are equivalent to DFF and TFF primitives without clear or preset inputs.
Note: The VHDL simulation model /usr/quartus/eda/synopsys/sim/vhdl/vital/flex.cmp file shows the exact cell and pin names for each device family. The Verilog HDL simulation file /usr/quartus/eda/synopsys/sim/verilog/altera/altera.v shows the functionality of these cells.
The following table lists the technology library names.
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