Assigning Design Constraints with the DC FPGA Software
Once you create a design in the Synopsys Design Compiler FPGA software, you can load the design and assign design constraints using the DC FPGA shell. You can also create a Tcl Script File (.tcl) or use the fpga_version user interface to perform the following tasks.
Elaborate the top-level design entity by typing the following command at the DC FPGA shell prompt:
elaborate<top-level design entity>
To specify the top-level entity and link the design files, at the DC FPGA shell prompt, type:
current_design<top-level design entity>
link
To select a target device for the project:
To display all devices for a specific device family, type set_fpga_target_device -show_all at the DC FPGA shell prompt.
To specify a device, type set_fpga_target_device<device name> at the DC FPGA shell prompt.
The DC FPGA software supports a subset of the Synopsys Design Constraints (SDC) timing constraints. You can use these commands to set timing constraints for the design entities in the design. You also create a Tcl Script File that contains the timing constraints for the design and apply it to the design by typing the following command at the DC FPGA prompt:
source<timing constraints file name>.tcl
For more information about using SDC timing constraints, refer to the Synopsys DC FPGA User Guide.
文档资料
> 
at the command prompt.
