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主页 > 支持 > 软件 > 综合工具 > FPGA Compiler II > Example of Creating a Black Box for a Verilog HDL Custom Megafunction Variation with the FPGA Compiler II Software 打印此页 发送此页 Example of Creating a Black Box for a Verilog HDL Custom Megafunction Variation with the FPGA Compiler II Software To specify that the FPGA Compiler II software should treat the lvds_rx_wrapper.v file that you created in Example of Creating a Verilog HDL Custom Variation of the altlvds_rx Function as a black box, refer to the following code sample from the top-level design file. In this example, the top-level design file is top_level_lvds.v. To modify the source code for the top_level_lvds.v file to define the module name and port type and to specify that the module is a black box, you can use the lvds_rx_wrapper_bb.v empty module declaration and add it to the top_level_lvds.v top-level design file as shown in the following code sample: // LVDS Top Level Function module top_level_lvds ( receiver_in,                   receiver_inclock,                   receiver_deskew,                   transmitter_out,                   transmitter_outclock ); input  [1:0]    receiver_in; input           receiver_inclock; input           receiver_deskew; output [1:0]    transmitter_out; output          transmitter_outclock; wire            rx_outclock; wire   [7:0]    rx_out; // rtl or glue logic // instantiate the lvds receiver wrapper lvds_rx_wrapper U0      (                           .rx_deskew (receiver_deskew),                           .rx_inclock (receiver_inclock),                           .rx_in (receiver_in),                           .rx_out (receiver_out),                           .rx_outclock (receiver_outclock)); // instantiate the lvds transmitter wrapper lvds_tx_wrapper U1 (                           .tx_in (receiver_out),                           .tx_inclock (receiver_outclock),                           .tx_out (transmitter_out),                           .tx_outclock (transmitter_outclock)); endmodule // module declarations for the instantiated components module lvds_rx_wrapper (   rx_in,   rx_inclock,   rx_deskew,   rx_outclock,   rx_out);   input   [1:0]  rx_in;   input          rx_inclock;   input          rx_deskew;   output         rx_outclock;   output  [7:0]  rx_out; endmodule module lvds_tx_wrapper (   tx_in,   tx_inclock,   tx_out,   tx_outclock);   input   [1:0]   tx_in;   input           tx_inclock;   output  [1:0]   tx_out;   output          tx_outclock; endmodule     给本页评分

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