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> Example of Performing a Functional Simulation of a FPGA Compiler II Verilog HDL Design with the FPGA Compiler II Software
You can create a script file that performs the following steps:
Compiles the altera_mf.v library.
Compiles the Verilog Design File (.v) generated by the MegaWizard Plug-In Manager with the ModelSim software. In this example, the file is lvds_rx_wrapper.v.
Compile the top-level Verilog Design File with the ModelSim software. In this example, the file name is top_level_lvds.v.
Compiles the test bench file. In this example, the test bench file name is test.v.
You can simulate this sample design in the ModelSim software by using the commands shown in the following sample script:
vlib work # Create working directory
vlog /quartus/eda/sim_lib/altera_mf.v # Read the simulation library
# /quartus/ is the path to Quartus II
exec vmap altera_mf work # Create altera_mf library and map it to work
vlog lvds_rx_wrapper.v lvds_tx_wrapper.v # Compile Megawizard generated file
vlog top_level_lvds.v # Compile source instantiating module
vlog test.v # Compile test fixture
vsim -t ns test # Simulate cam_wrapper_test with
# resolution in ns
view wave
add wave /*
run 10000 ns
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