Assign Design Constraints and Optimize the Design with the FPGA Compiler II Software
When you assign design constraints in the Synopsys FPGA Compiler II software you can set global optimization goals and CPU effort designations, and assign pins, logic options, and timing constraints. You can assign pins, logic options, and timing constraints to a design in Synopsys FPGA Compiler II constraint tables. Some design-specific information is extracted automatically from your design and displayed in the constraint tables; you can also manually make specific assignments in these tables. All design-specific information, such as clock names, port names, and design hierarchy assignments is extracted automatically from the design.
To assign design constraints in the Synopsys FPGA Compiler II software:
To set global optimization controls in the FPGA Compiler II software, perform the following steps:
Note: The Synopsys FPGA Compiler II software allows you to choose either speed or area options and to specify either high, low, or fast CPU effort in logic optimization. Optimization goals are set on a global basis or on particular levels of hierarchy.
If you have not already done so, identify the top-level design for your project in the Design Sources window. Select the top-level design from the Identify top-level design list on the toolbar. The Create Implementation dialog box appears.
Under Optimize for, select Speed or Area to specify the optimization goal for the entire design:
The Speed option minimizes delay by synthesizing circuits to contain the least number of levels of combinational logic, sometimes yielding increased design area. This setting maximizes operating frequency and minimizes combinational path delays.
The Area option minimizes the combinational logic resources used, sometimes yielding reduced speed. This setting minimizes combinational logic usage.
Under Effort, select on High, Low, or Fast to specify the CPU effort level.
The Low option increases compilation speed at the expense of larger combinational area. This option is most useful for minimizing compilation time for very large designs when neither speed nor area are critical.
The High option decreases the combinational area at the expense of compilation speed. This option is recommended in speed- or area-critical designs.
The Fast option optimizes for both area and effort.
If you want to preserve the design hierarchy, turn on Preserve Hierarchy.
If you do not want to enter any design constraints, turn on Skip constraint entry.
To set optimization goals on a particular level of hierarchy, perform the following steps:
Note: You can set the same optimization controls on individual levels of hierarchy for greater control. This strategy is useful when your design contains hierarchical blocks with different requirements. For example, some blocks may be time-critical while others are not. To obtain the best results, you should optimize time-critical blocks for speed and other blocks for area. Optimization settings are the same for an entire design file, regardless of its level of hierarchy.
In the Chips window, expand the preoptimized chip icon.
Right-click on the design name, and click Edit Constraints to display the constraints tables.
Click the Modules tab.
Find the row that displays the level of hierarchy for which you want to set an optimization goal.
In the Optimize for column, select Speed or Area.
In the Effort column, select High, Low, or Fast.
To make resource assignments:
Right-click the design implementation icon in the Chips window, and then click Edit Constraints command to display the Altera-specific constraint tables. These tables allow you to specify resource assignments for your design. All design-specific information such as clock names, port names, and design hierarchy is extracted automatically from the design. Altera recommends entering specific requirements directly into these tables to obtain the desired optimization.
Make assignments in the appropriate constraint tables. You can click a tab to toggle between tables. Refer to the following table, which shows the available Quartus II resource assignment options in the FPGA Compiler II constraint tables. The Clock and Paths tabs already contain information that you previously entered in the Create Implementation dialog box.
Quartus II Resource Assignment
FPGA Compiler II ConstraintTab Name
FPGA Compiler IIAction
Pin assignment
Ports
Specify the pin number in the Pad Loc column.
tSU timing assignment
Ports
Specify the time in the Input Delay column.
tCO timing assignment
Ports
Specify the time in the Output Delay column.
Slow Slew Rate logic option assignment
Ports
Click the appropriate cell in the Slew Rate column and select <default>, FAST, or SLOW from the list.
Fast I/O logic option assignment
Ports
Click the appropriate cell in the Use I/O Reg column and select <default>, ON, or OFF in the list.
tPD timing assignment
Ports
Specify the time in the Req. Delay column.
Close the window and click Yes to save the changes to the constraint table.
To optimize the design, select the design implementation icon in the Project window and click the Optimize button on the toolbar. A new optimized implementation icon appears beneath the original implementation icon. When you open the optimized implementation, the constraint tables are back-annotated with the optimization results. The FPGA Compiler II software optimizes a design for either speed or area.
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