Enter a VHDL or Verilog HDL design in the Quartus II Text Editor or another standard text editor and save it in your working directory.
Describe your design using FPGA Compiler II-supported Verilog HDL or VHDL constructs. For information on synthesizable Verilog HDL or VHDL constructs, refer to the online HDL Reference Manual provided with the FPGA Compiler II software. The Quartus II software supports all LPM functions except the truth table, finite state machine, and pad functions. The FPGA Compiler II software supports all LPM megafunctions that are supported in the Quartus II software except the lpm_and, lpm_or, lpm_xor, and lpm_mux functions.
To use megafunctions in the design, use the MegaWizard Plug-In Manager to generate and instantiate a megafunction variation. You can use the MegaWizard Plug-In Manager to create content-addressable memory (CAM), ClockLock PLL, LVDS, or RAM functions. The following topics show how to create and instantiate some of these functions.
Note: You can instantiate MegaCore functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP). The OpenCore feature in the Quartus II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.
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