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主页 > 支持 > 软件 > 综合工具 > FPGA Compiler II 打印此页 发送此页 About Using the FPGA Compiler II Software with the Quartus II Software You can use the Synopsys FPGA Compiler II design entry/synthesis tool to create, synthesize, and optimize a project and then generate an EDIF Input File (.edf) for compilation in the Quartus II software. The following topics describe the typical flow with the FPGA Compiler II software and the Quartus II software: Set up the FPGA Compiler II working environment Create a design for use with the FPGA Compiler II software Set up a project with the FPGA Compiler II software Assign design constraints and optimize the design with the FPGA Compiler II software Generate EDIF Netlist Files with the FPGA Compiler II software Analyze design results with the FPGA Compiler II software You can also run the FPGA Compiler II software automatically from within the Quartus II software to synthesize a design using the NativeLink feature. You can use Altera-provided megafunctions in EDA tools by using the MegaWizard Plug-In Manager to create custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions. Refer to the following topics for information on how to use specific megafunctions. You can use the same procedures and principles to use similar megafunctions in other designs:. Creating and Instantiating a Verilog HDL Function for Use with the FPGA Compiler II Software Creating and Instantiating a Verilog HDL RAM Function for Use with the FPGA Compiler II Software Creating and Instantiating a VHDL Function for Use with the FPGA Compiler II Software More information is available on other EDA design entry/synthesis tools on the Altera website.     给本页评分

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