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> Example of Performing a Functional Simulation of a Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software
You can create a script file that performs the following steps:
Compiles the altera_mf.v library.
Compiles the Verilog Design File (.v) generated by the MegaWizard Plug-In Manager. In this example, the file is cam_wrapper_v.v.
Compiles the top-level Verilog Design File with the ModelSim software. In this example, the file is camsource.v.
Compiles the test bench file. The following sample code is for a sample test bench file that can be used in this example. The test bench file name is cam_wrapper_test.v.
Compiles the memory initialization files. The following sample files, my_cam.hex and my_cam_xu.hex, are examples of the memory initialization files that can be used in this example.
You can simulate this sample design in the ModelSim software by typing in the following commands:
vlib work # Create working directory
vlog /quartus/eda/sim_lib/220model.v # Compile the lpm library
vlog /quartus/eda/sim_lib/altera_mf.v # Compile the altera_mf library
exec vmap lpm work # Create lpm library and map it to work
exec vmap altera_mf work # Create altera_mf library and map it to work
vlog cam_wrapper_v.v # Compile Megawizard generated file
vlog camsource.v # Compile source instantiating module
vlog cam_wrapper_test.v # Compile test fixture
vsim -t ns cam_wrapper_test # Simulate cam_wrapper_test with
# resolution in ns
view wave
add wave /*
run 10000 ns