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Example of Performing a Functional Simulation of a Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software

You can perform a functional simulation of the custom megafunction variation you created in Example of Creating a Black Box for a Verilog HDL Custom Variation of a Megafunction before compilation in the LeonardoSpectrum or the Quartus II software.

You can create a script file that performs the following steps:

  • Compiles the altera_mf.v library.

  • Compiles the Verilog Design File (.v) generated by the MegaWizard Plug-In Manager. In this example, the file is cam_wrapper_v.v.

  • Compiles the top-level Verilog Design File with the ModelSim software. In this example, the file is camsource.v.

  • Compiles the test bench file. The following sample code is for a sample test bench file that can be used in this example. The test bench file name is cam_wrapper_test.v.

Cam_wrapper_test.v

`timescale 1 ns / 1 ns
module cam_wrapper_test();
wire [31:0] pattern;
reg [4:0] wraddress;
reg wren; reg [31:0] wrx;
reg wrxused;
reg wrdelete;
reg inclock;
reg inclocken;
reg inaclr;
wire [4:0] maddress;
wire mfound;
wire [4:0] mcount;
wire rdbusy;
wire wrbusy;
reg [31:0] cnt;
reg clock_count;
camsource L0(.pattern(pattern), .wrx(wrx), .wrxused(wrxused), .wrdelete(wrdelete), .wraddress(wraddress), .wren(wren), .inclock(inclock), .maddress(maddress), .mfound(mfound), .mcount(mcount), .rdbusy(rdbusy),.wrbusy(wrbusy), .inclocken(inclocken));
initial
begin
assign inclocken = 1'b1;
wrx = 8'b00000000;
wrxused = 1'b0;
wrdelete = 1'b0;
inaclr = 1'b1;
wren = 1'b0;
initial cnt = 0;
end assign pattern = cnt;
initial
begin
inclock = 1'b0;
forever #5 inclock = ~inclock;
end
initial
begin
clock_count = 1'b0;
forever #50 clock_count = ~clock_count;
end
always@(posedge clock_count)
begin
cnt = cnt + 1;
end
endmodule

  • Compiles the memory initialization files. The following sample files, my_cam.hex and my_cam_xu.hex, are examples of the memory initialization files that can be used in this example.

my_cam.hex

:0400000000000057a5
:0400010000000012e9
:040002000000005aa0
:040003000000005d9c
:0400040000000015e3
:0400050000000054a3
:0400060000000018de
:040007000000001bda
:0400080000000003f1
:0400090000000006ed
:04000a0000000036bc
:04000b0000000033be
:04000c0000000039b7
:04000d00000000519e
:04000e000000003cb2
:04000f000000001ecf
:0400100000000021cb
:040011000000003caf
:0400120000000009e1
:0400130000000042a7
:040014000000003fa9
:040015000000004e99
:040016000000000cda
:040017000000000fd6
:04001800000000459f
:040019000000002db6
:04001a0000000030b2
:04001b000000004899
:04001c000000004b95
:04001d000000002ab5
:04001e0000000027b7
:04001f0000000024b9
:00000001ff

my_cam_xu.hex

:0400000000000000fc
:0400010000000000fb
:0400020000000000fa
:0400030000000000f9
:0400040000000000f8
:0400050000000000f7
:0400060000000000f6
:0400070000000000f5
:0400080000000000f4
:0400090000000000f3
:04000a0000000000f2
:04000b0000000000f1
:04000c0000000000f0
:04000d0000000000ef
:04000e0000000000ee
:04000f0000000000ed
:0400100000000000ec
:0400110000000000eb
:0400120000000000ea
:0400130000000000e9
:0400140000000000e8
:0400150000000000e7
:0400160000000000e6
:0400170000000000e5
:0400180000000000e4
:0400190000000000e3
:04001a0000000000e2
:04001b0000000000e1
:04001c0000000000e0
:04001d0000000000df
:04001e0000000000de
:04001f0000000000dd
:00000001ff

You can simulate this sample design in the ModelSim software by typing in the following commands:


vlib work                                       # Create working directory
vlog /quartus/eda/sim_lib/220model.v            # Compile the lpm library
vlog /quartus/eda/sim_lib/altera_mf.v           # Compile the altera_mf library
exec vmap lpm work                              # Create lpm library and map it to work
exec vmap altera_mf work                        # Create altera_mf library and map it to work
vlog cam_wrapper_v.v                            # Compile Megawizard generated file
vlog camsource.v                                # Compile source instantiating module
vlog cam_wrapper_test.v                         # Compile test fixture
vsim -t ns cam_wrapper_test                     # Simulate cam_wrapper_test with
                                                # resolution in ns
view wave
add wave /*
run 10000 ns

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