Assigning Design Constraints with the LeonardoSpectrum Software

To specify assign design constraints in the LeonardoSpectrum software:

1. If you have not already done so, set up a project with the LeonardoSpectrum software.

2. Click the Constraints tab.

3. At the bottom of the Constraints tab, click one or more of the following tabs to specify different constraints:

    

   Tab Name	Description
   Global tab	Specifies constraints for the entire design, such as clock frequency, clock cycle, minimum delays, or global path groups.
   Clock tab	Specifies the characteristics of different clocks in the design. Clock specifications include the clock cycle or frequency, pulse width or duty cycle, and clock offset.
   Input tab	Specifies the input arrival time and drive characteristics for each input port.
   Output tab	Specifies the output required time and load characteristics for each output port.
   Signal tab	Specifies signals to be preserved during optimization.
   Module tab	Specifies the instance constraints. These are Don't Touch, Optimize for area or delay, and standard or quick Effort.
   Path tab	Specifies paths by selecting start points (input ports and registers) and end points (output ports and registers). You can also specify false paths and multicycle paths.
   Report tab	Generates a report of the constraints, loads an existing constraint file, or saves current constraints to a file.

    

4. In the Constraints tab, click Apply.

5. To continue with the LeonardoSpectrum design flow, generate EDIF Netlist Files with the LeonardoSpectrum software.