文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计

产品    Quartus II       SOPC Builder       MAX+PLUS II       ModelSim-Altera     资源中心       简介       安装&许可       脚本        电路板设计& I/O       网表阅读器 & 综合       编译增强特性       优化       功耗管理    TimeQuest时序分析器       标准时序分析器       仿真 & 确认       片内调试       HardCopy设计     软件资源       操作系统支持       驱动安装     下载与许可       下载    许可     Quartus II EDA 支持       Quartus II 接口    综合工具           Design Compiler           DC FPGA           FPGA Compiler II           LeonardoSpectrum           Precision RTL Synthesis           Synplify    仿真工具    验证工具    时序分析工具    再综合工具    电路板级工具     老版软件EDA支持       供应商类       工具类       功能类

主页 > 支持 > 软件 > 综合工具 > Precision RTL Synthesis > Assigning Design Constraints with the Precision RTL Synthesis Software 打印此页 发送此页 Assigning Design Constraints with the Precision RTL Synthesis Software You assign design constraints in the Precision RTL synthesis software by creating a Synopsys Design Constraints File (.sdc) that contains the design constraints and adding it to the project. You can also set design constraints in the Precision RTL Synthesis software. The Precision RTL Synthesis software then creates a <design name>_constraints.sdc Synopsys Design Constraint File in the current project directory. To set design constraints in the Precision RTL Synthesis software user interface: If you have not already done so, set up a project with the Precision RTL Synthesis software. To create clock(s) for the design and set clock attributes: In the Design Hierarchy window, click the + icon to expand the Clocks folder. To create a clock and set clock constraints for a specific clock, right-click on the clock, and click Set Clock Constraints. To set additional attributes for a specific clock, right-click on the clock, and click Set Attributes. To set timing and mapping constraints on ports: In the Design Hierarchy window, expand the Ports folder. Expand the Inputs or Outputs folder. Right-click a specific port and click Set Input Constraints or Set Output Constraints. The Port Constraints dialog box appears. Use the Port Constraints dialog box to set timing and mapping constraints, including pin numbers, I/O standards, and I/O pads. You can also right-click on a specific port and click Force Register into I/O to force registers to be moved into I/O elements during synthesis. To disable I/O pad insertion on I/O pins in the design during synthesis: Click Set Options. The Synthesis Options dialog box appears. Select Optimization. Turn off Add IO Pads. Click OK. To continue with the Precision RTL Synthesis design flow, generate EDIF Netlist Files with the Precision RTL Synthesis software.     给本页评分

请填写反馈意见   注册索取最新邮件通知

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  mySupport | 器件 | 软件 | IP | 设计范例 | 参考设计  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。