Creating a Design for Use with the Precision RTL Synthesis Software
You can create VHDL and Verilog HDL design files with the Quartus II Text Editor or another standard text editor for use with the Mentor Graphics Precision RTL Synthesis software.
To create a Verilog HDL or VHDL design file for use with the Precision RTL Synthesis software:
Enter a VHDL or Verilog HDL design in the Quartus II Text Editor or another standard text editor and save it in your working directory.
To use megafunctions in a design, use the MegaWizard Plug-In Manager to generate and instantiate a megafunction variation. You can use the MegaWizard Plug-In Manager to create content-addressable memory (CAM), ClockLock PLL, LVDS, or RAM functions. Refer to the Creating and Instantiating Altera-Provided Functions in Other EDA Tools topic for examples on how to use Altera-provided megafunctions and library of parameterized modules (LPM) functions in other EDA design entry/synthesis tools.
In addition, the Precision RTL Synthesis software automatically recognizes certain types of HDL code and maps them to Altera megafunctions during synthesis. You can describe the design in Verilog HDL or VHDL and use the Precision RTL Synthesis software to infer multipliers, multiply-accumulators, multiply-adders, RAM, and ROM functions directly from HDL code.
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