Example of Creating a Black Box for a VHDL Custom Variation of a Megafunction with the Synplify Software
To specify that the Synplicity Synplify software should treat the my_pll.vhd file that you created in Example of Creating a VHDL Custom Variation of the altclklock Function as a black box, refer to the following code sample from the top-level design file. In this example, the top-level design file is pllsource.vhd. To modify the source code for the pllsource.vhd file to define the module name and port type and to specify that the module is a black box, add an empty module declaration to the pllsource.vhd top-level design file as shown in the following code sample:
library IEEE;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
ENTITY pllsource IS
PORT(
inclock, inclocken : in std_logic;
data_in1 : in std_logic_vector(7 downto 0);
clock0, locked, div2 : out std_logic;
r_out : out std_logic_vector(7 downto 0));
END pllsource;
ARCHITECTURE rtl of pllsource IS
component my_pll
PORT
(
inclock : IN STD_LOGIC ;
inclocken : IN STD_LOGIC ;
locked : OUT STD_LOGIC ;
clock0 : OUT STD_LOGIC ;
clock1 : OUT STD_LOGIC
);
end component;
attribute black_box of my_pll: component is true;
SIGNAL clock1_sig : std_logic;
SIGNAL r_int : std_logic_vector(7 downto 0);
BEGIN
my_pll_inst : my_pll PORT MAP (
inclock => inclock,
inclocken => inclocken,
locked => locked,
clock0 => clock0,
clock1 => clock1_sig
);
PROCESS(clock1_sig)
begin
if (clock1_sig'event and clock1_sig='1') then
r_int <= data_in1;
r_out <= r_int;
end if;
end process;
END rtl;
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