Example of Creating a VHDL Custom Variation of the altclklock Function
The following example procedure illustrates how to use the MegaWizard Plug-In Manager to create a custom megafunction variation of the altclklock function. You can follow similar steps to create custom megafunction variations of other megafunctions. To create a custom megafunction variation of the altclklock function:
On the Tools menu, click MegaWizard Plug-In Manager.
In the MegaWizard Plug-In Manager, in response to Which action do you want to perform?, select Create a new custom megafunction variation and click Next.
In response to Which type of output file do you want to create?, select VHDL.
In the Available Megafunctions list, expand the I/O folder and select ALTCLKLOCK.
In response to What name do you want for the file?, type the appropriate file name or browse click to select the appropriate location. For this example, the path and file name should be C:\synplify_e_features\vhdl\pll\my_pll.vhd.
Click Next.
To select the device family which your function targets and to specify related options:
For this example, select APEX 20KE in response to Use which device family?
Under Which optional ports are needed?, turn on locked and inclocken.
Under How should the PLL output(s) be generated?, turn on Use the feedback path inside the PLL and specify a value of 0 degrees for with a programmed phase shift of.
Click Next.
Note: The remaining options are family dependent. The MegaWizard Plug-In Manager guides you to choose valid options for the selected device family.
To specify the input clock frequency and the clock output multiplication and division factors:
In response to What is the input clock frequency?, select 40.0 MHz.
In response to Which output clocks would you like to use?, select Clock0 and Clock1, using the clock multiplication and division factors in the table below.
Options:
Clock0
Clock1
Clock multiplication factor
4
2
Clock division factor
1
1
Click Next.
To specify the number of cycles to achieve lock and to lose lock:
In response to How many synchronized clock cycles should pass before PLL is considered locked?, select 2.5 clock cycles.
In response to How many unsynchronized clock cycles should pass before PLL is considered to have lost its lock?, select 2.5 clock cycles.
Click Next.
The Summary page informs you of the files that the MegaWizard Plug-In Manager creates. In this example, it generates the following files:
The following sample shows the my_pll.vhd file, which can be generated by the MegaWizard Plug-In Manager. The my_pll.vhd file contains an instantiation and parameters of the altclklock function.
-- megafunction wizard: %ALTCLKLOCK%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclklock
-- ============================================================
-- File Name: my_pll.vhd
-- Megafunction Name(s):
-- altclklock
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY my_pll IS
PORT
(
inclock : IN STD_LOGIC ;
inclocken : IN STD_LOGIC ;
locked : OUT STD_LOGIC ;
clock0 : OUT STD_LOGIC ;
clock1 : OUT STD_LOGIC );
END my_pll;
ARCHITECTURE SYN OF my_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT altclklock
GENERIC (
inclock_period : NATURAL;
clock0_boost : NATURAL;
clock1_boost : NATURAL;
operation_mode : STRING;
intended_device_family : STRING;
valid_lock_cycles : NATURAL;
invalid_lock_cycles : NATURAL;
valid_lock_multiplier : NATURAL;
invalid_lock_multiplier : NATURAL;
clock0_divide : NATURAL;
clock1_divide : NATURAL;
outclock_phase_shift : NATURAL
);
PORT (
inclocken : IN STD_LOGIC ;
inclock : IN STD_LOGIC ;
clock0 : OUT STD_LOGIC ;
clock1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
clock0 <= sub_wire0;
clock1 <= sub_wire1;
locked <= sub_wire2;
altclklock_component : altclklock
GENERIC MAP (
inclock_period => 25000,
clock0_boost => 4,
clock1_boost => 2,
operation_mode => "NORMAL",
intended_device_family => "APEX20KE",
valid_lock_cycles => 5,
invalid_lock_cycles => 5,
valid_lock_multiplier => 5,
invalid_lock_multiplier => 5,
clock0_divide => 1,
clock1_divide => 1,
outclock_phase_shift => 0
)
PORT MAP (
inclocken => inclocken,
inclock => inclock,
clock0 => sub_wire0,
clock1 => sub_wire1,
locked => sub_wire2
);
END SYN;
To close the MegaWizard Plug-In Manager, click Finish.
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