To perform a functional simulation in the ModelTech Modelsim software, you can create a script that performs the following steps:
Compiles the altera_mf.v library.
Compiles the Verilog Design File (.v) generated by the MegaWizard Plug-In Manager. In this example, the file is my_pll.v.
Compiles the top-level Verilog Design File. In this example, the file name is pllsource.v.
Compiles the test bench file. In this example, the test bench file name is plltest.v.
You can simulate this sample design in the ModelSim software by using the commands shown in the following sample script:
vlib work # Create working directory
vlog /quartus/eda/sim_lib/altera_mf.v # Compile the altera_mf library
exec vmap altera_mf work # Create altera_mf library and map it to work
vlog my_pll.v # Compile Megawizard generated file
vlog pllsource.v # Compile source instantiating module
vlog plltest.v # Compile test bench file
vsim -t ps work.plltest # Simulate plltest with resolution in ps
add wave /plltest/* # Add the port signals to the waveform view
add wave /plltest/U1/PLL_1/altclock_component/clock1 # Add the clock1 altclklock signal to the
# waveform view
run 1000 ns # Run the simulation for 1000 ns
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