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> Example of Performing a Timing Simulation of a Synplicity VHDL Design with a Custom Megafunction Variation with the ModelSim Software
Example of Performing a Timing Simulation of a Synplicity VHDL Design with a Custom Megafunction Variation with the ModelSim Software
To perform a timing simulation on your Synplify VHDL design using the ModelSim software once you compile your design in the Quartus II software, you can create a script that performs the following steps:
Compiles the <device family>_atoms.vhdand<device family>_components.vhd libraries.
Compiles the VHDL Output File (.vho) the Quartus II software generates during compilation. In this example, the VHDL Output File is plldesign.vho.
Compiles the test bench file. In this example, the test bench file name is plltest.vho.
You can simulate the sample design in the ModelSim software by using the commands shown in the following sample script:
vlib work # Create working directory
vcom /quartus/eda/sim_lib/apex20ke_atoms.vhd # Read the simulation library
vcom /quartus/eda/sim_lib/apex20ke_components.vhd # Read the simulation library
# /quartus/ is the path to Quartus II
vmap apex20ke work # Map the family name to work library
vcom plldesign.vho # Compile the VHDL Output File
vcom plltest.vhd # Compile test fixture
vsim -t ps work.plltest(behave) # Simulate plltest with resolution in ps
add wave /plltest/* # Add the port signals to the waveform view
run 1000 ns # Run the
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