Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software
You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synplicity Synplify and Quartus II software. This procedure shows only how to instantiate a ClockLock PLL function using Verilog HDL; however, you can use similar procedures to instantiate other Altera-provided functions.
Note: If you want to use the lpm_mult, lpm_ram_dp, lpm_ram_dq, lpm_rom, lpm_latch, or lpm_ff library of parameterized modules (LPM) functions, refer to the Creating a Design for Use with the Synplify Software topic.
Open the MegaWizard Plug-In Manager and specify appropriate options for the megafunction you want to instantiate.
The MegaWizard Plug-In Manager generates custom megafunction variations that are based on Altera-provided functions, including library of parameterized modules (LPM) functions, as well as Altera megafunctions.
Refer to the following example to create a Verilog HDL custom megafunction variation of the altclklock function:
To prepare the Verilog HDL design for synthesis with the Synplify software, you must specify that the Synplify software should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The Synplify software then makes the correct connections to the ports in the Verilog HDL output netlist file (.vqm). The Quartus II software reads in the Verilog HDL netlist file as a Verilog Quartus Mapping File (.vqm) and processes the instantiated megafunction. The MegaWizard Plug-In Manager also generates a file with the extension _bb.v that can be used as an empty module declaration for use as a black box. To specify that the Synplify software should treat the design file for the megafunction as a "black box," refer to the following example:
Note: The design file generated by the MegaWizard Plug-In Manager must be in the same directory as the VQM File or added to the Quartus II project.
If necessary, perform a functional simulation of the design using an EDA simulation tool. Refer to the following example for instructions and a sample script used in performing a functional simulation:
If you have not already done so, create a new project or open an existing project.
Compile the design in the Quartus II software.
If necessary, performing a timing simulation with the ModelSim software or simulate the design with another Verilog HDL simulation tool. Refer to the following example for instructions and a sample script used in performing the timing simulation:
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