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Generating Verilog Quartus Mapping Files with the Synplify Software

To generate Verilog Quartus Mapping Files (.vqm) in the Synplicity Synplify software for use with the Quartus II software:

  1. If you have not already done so. assigning design constraints with the Synplify software.

  2. To run the Synplify software, click Run. The Synplify software synthesizes and optimizes the design, and creates a Verilog Quartus Mapping File.

  3. Correct any errors or warnings.

  4. If you correct any errors or warnings, or add timing requirements to your design, repeat step 2 to run the Synplify software and implement the changes in the Synplify-synthesized design.

Note: Altera recommends that you store the result file in a separate directory from the source files. Make sure to copy any VHDL or Verilog HDL files (or black boxes) to this directory.

  1. Create the \<project directory>\quartus directory.

  2. Copy the <design name>.vqm, <design name>.tcl and black box files generated in step 2 to the \<project directory>\quartus directory.

  3. After you create and load the project in the Quartus II software, run the Synplify-generated Tcl Script File in the Quartus II software.

  4. Compile the design with the Quartus II software.

  5. To continue with the Synplify design flow, analyzing design results with the Synplify software.

 

 

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