To run the Synplify software, click Run. The Synplify software synthesizes and optimizes the design, and creates a Verilog Quartus Mapping File.
Correct any errors or warnings.
If you correct any errors or warnings, or add timing requirements to your design, repeat step 2 to run the Synplify software and implement the changes in the Synplify-synthesized design.
Note: Altera recommends that you store the result file in a separate directory from the source files. Make sure to copy any VHDL or Verilog HDL files (or black boxes) to this directory.
Create the \<project directory>\quartus directory.
Copy the <design name>.vqm, <design name>.tcl and black box files generated in step 2 to the \<project directory>\quartus directory.
After you create and load the project in the Quartus II software, run the Synplify-generated Tcl Script File in the Quartus II software.