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主页 > 支持 > 软件 > 时序分析工具 > PrimeTime > Performing Timing Verification with the PrimeTime Software 打印此页 发送此页 Performing Timing Verification with the PrimeTime Software To perform a timing verification of a Quartus II–generated Verilog Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Synopsys PrimeTime software: If you have not already done so, set up the PrimeTime working environment. To generate the Verilog Output File and corresponding SDF Output File: Specify EDA tool settings in the Quartus II software. Compile the design with the Quartus II software. Note: During compilation, the Quartus II software generates a <design name>_pt_v.tcl Tcl Script File (.tcl), which sets up the PrimeTime environment for performing a timing verification, and places it in the \<project directory>\timing\primetime\ directory. The TCL Script File contains: External input and output clock delays User-created base clocks and derived clocks PLL clocks Single point and two point CUT paths, exported in the Tcl Script File as set_false_path commands Multicycle path constraints using the set_multicycle_path command If you specified settings in the HardCopy Settings page of the Settings dialog box before compilation, the Quartus II software generates a HardCopy file, <current project name>_pt_hcpy_v.tcl, and places in the \<current project>\hardcopy directory. You can use this Tcl Script File for timing verification with the PrimeTime software. To generate a Verilog Output File and corresponding SDF Output File with minimum timing values: Specify EDA tool settings in the Quartus II software. Compile the design with the Quartus II software. On the Processing menu, point to Start, and then click Start Classic Timing Analyzer (Fast Timing Model) to perform a minimum timing analysis. On the Processing menu, point to Start, and then click Start EDA Netlist Writer to generate the output netlist files. Note: The EDA Netlist Writer generates a <design name>_fast.vo Verilog Output File and places it in the specified output directory. The default location is <project directory>\timing\primetime\. To start the PrimeTime software in command-line mode, type pt_shell  at the command prompt. Source the Tcl Script File by typing source <design name>_pt_(v | vhd).tcl  at the PrimeTime shell prompt. To set the mode of operation for the PrimeTime memory models for RAM ATOMs, use either the read_during_write mode or the no_read_during_write mode (the default is read_during_write) by typing one of the following commands at the PrimeTime shell prompt: Device Family Commands for Setting the Mode of Operation APEX 20K, APEX 20KC, and APEX 20KE set_mode read_during_write | no_read_during_write *.apexmem  APEX II set_mode read_during_write | no_read_during_write *.apexiimem  ACEX 1K or FLEX 10KE set_mode read_during_write | no_read_during_write *.flex10kemem  Mercury set_mode read_during_write | no_read_during_write *.mercurymem  Perform a timing verification with the PrimeTime software.     给本页评分

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